riscv-isa-release-61b2ce9-2024-02-29

This release was created by: wmat
Release of RISC-V ISA, built from commit 61b2ce9, is now available.

What's Changed

• fix typo by @Phantom1003 in #1138
• Fix typo by @lpha-z in #1145
• Fix journal name typo by @visitorckw in #1146
• Fix typo and missing by @yf13 in #1152
• Fix wrong bit length of rd field by @404allen404 in #1153
• Define hardware error exception cause code by @aswaterman in #1105
• Specify SFENCE/HFENCE requirements when changing PBMTE by @aswaterman in #1111
• Bump supervisor ISA version to 1.13-draft by @aswaterman in #1110
• Clarify constraints on when tval might be zeroed by @aswaterman in #1108
• Define the RV32-only medelegh CSR by @aswaterman in #1109
• delete user-mode interrupt notes in mtvec register section by @yf13 in #1159
• Fix typo: "Sv38" => "Sv48" by @OccupyMars2025 in #1162
• Application to RISC-V on adding new marchid for CV-Wally from Harvey … by @stineje in #1164
• Fix MODE field description of mtvec register by @HepoH3 in #1165
• Add PMM field to *envcfg and mseccfg by @aswaterman in #1170
• Specify that the supervisor physical address is divided by 4 KiB by @charlie-rivos in #1177
• Add marchid for Boa-RISC-V (on the correct branch this time) by @robotman2412 in #1182
• Add marchid for WIV64 by @StartForKiller in #1183
• marchid allocation request for RV6 by @kiclu in #1184
• Add marchid for ApogeoRV by @GabbedT in #1185
• Add marchid for MicroRV32 by @saahm in #1188
• Delete word with inconsistency by @demin-han in #1189
• fix broken alloy link by @kbroch-rivosinc in #1202
• Redefine MXL to be read-only by @aswaterman in #1204
• Add note to guide trap handler design by @ved-rivos in #1208
• Clarifications to the Addressing and Memory Protection section by @ved-rivos in #1142
• Attempts to access non-existent CSRs are reserved by @aswaterman in #1207
• Remove Zam; define misaligned atomicity granule PMA by @aswaterman in #1206
• Incorporate Svadu and Svade specs by @aswaterman in #1209
• Add a QEMU architecture ID by @palmer-dabbelt in #1213
• Add clarifying non-normative comments about [m]time by @aswaterman in #1210
• Don't conflate hart and system by @pdonahue-ventana in #1215
• Hardware Error exception priority by @ved-rivos in #1223
• added KianV RISC-V marchID by @splinedrive in #1228
• Zawrs - Wait-on-Reservation-Set chapter integration. by @wmat in #1217
• Fixes for H extension status diagrams by @sorear in #1238
• a typo by @OccupyMars2025 in #1240
• Fix typo: Quotation mark formatting mismatch in intro.adoc. by @Yakkhini in #1243
• Adding Base Cache Management Operation ISA Extensions chapter. by @wmat in #1226
• Clarify when SFENCE.W.INVAL/SFENCE.INVAL.IR are legal by @aswaterman in #1246
• Explicitly allow side effects for a failed SC by @sorear in #1239
• Add new Action to Release a new ISA when merging a PR by @rpsene in #1247
• Update merge-and-release.yml by @rpsene in #1250

New Contributors

• @Phantom1003 made their first contribution in #1138
• @lpha-z made their first contribution in #1145
• @visitorckw made their first contribution in #1146
• @yf13 made their first contribution in #1152
• @404allen404 made their first contribution in #1153
• @OccupyMars2025 made their first contribution in #1162
• @stineje made their first contribution in #1164
• @HepoH3 made their first contribution in #1165
• @robotman2412 made their first contribution in #1182
• @StartForKiller made their first contribution in #1183
• @kiclu made their first contribution in #1184
• @GabbedT made their first contribution in #1185
• @saahm made their first contribution in #1188
• @demin-han made their first contribution in #1189
• @kbroch-rivosinc made their first contribution in #1202
• @splinedrive made their first contribution in #1228
• @Yakkhini made their first contribution in #1243

Full Changelog: 2023-10-02...riscv-isa-release-61b2ce9-2024-02-29