Fix MODE field description of mtvec register #1165
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Fix MODE field description in the mtvec register In Section 1.6, "Exceptions, Traps, and Interrupts" of the unprivileged specification, a distinction is made between exceptions and interrupts. Table 13 in the privileged specification uses the term "exceptions" as a catch-all expression, encompassing both "exceptions and interrupts" which may not be immediately apparent. Reading "exceptions" merely as "exceptions" initially led me to believe that the 0th bit is used to control exception handling behavior, while the 1st bit is used to control interrupt handling behavior. Signed-off-by: Andrei Solodovnikov <[email protected]>
aswaterman
approved these changes
Nov 22, 2023
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Fix MODE field description in the mtvec register
In Section 1.6, "Exceptions, Traps, and Interrupts" of the unprivileged specification, a distinction is made between exceptions and interrupts.
Table 13 in the privileged specification uses the term "exceptions" as a catch-all expression, encompassing both "exceptions and interrupts" which may not be immediately apparent.
Reading "exceptions" merely as "exceptions" while seeing following word "interrupts" can led to believe that the 0th bit is used to control exception handling behavior, while the 1st bit is used to control interrupt handling behavior.