Define the RV32-only hedelegh CSR

src/hypervisor.adoc

@@ -272,9 +272,11 @@ same endianness as HS-mode.
 
 ==== Hypervisor Trap Delegation Registers (`hedeleg` and `hideleg`)
 
-Registers `hedeleg` and `hideleg` are HSXLEN-bit read/write registers,
-formatted as shown in <<hedelegreg>> and
-<<hidelegreg>> respectively. By default, all traps at
+Register `hedeleg` is a 64-bit read/write register, formatted as shown in
+<<hedelegreg>>.
+Register `hideleg` is an HSXLEN-bit read/write register, formatted as shown in
+<<hidelegreg>>.
+By default, all traps at
 any privilege level are handled in M-mode, though M-mode usually uses
 the `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode. The
 `hedeleg` and `hideleg` CSRs allow these traps to be further delegated
@@ -303,6 +305,10 @@ Requiring that certain bits of `hedeleg` be writable reduces some of the
 burden on a hypervisor to handle variations of implementation.
 ====
 
+When XLEN=32, `hedelegh` is a 32-bit read/write register
+that aliases bits 63:32 of `hedeleg`.
+Register `hedelegh` does not exist when XLEN=64.
+
 An interrupt that has been delegated to HS-mode (using `mideleg`) is
 further delegated to VS-mode if the corresponding `hideleg` bit is set.
 Among bits 15:0 of `hideleg`, bits 10, 6, and 2 (corresponding to the

src/images/bytefield/hedelegreg.edn

@@ -7,11 +7,11 @@
 (def right-margin 30)
 (def boxes-per-row 32)
 
-(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}})
+(draw-box "63" {:span 16 :text-anchor "start" :borders{}})
 (draw-box "0" {:span 16 :text-anchor "end" :borders{}})
 
 (draw-box "Synchronous Exceptions" {:span 18 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
 (draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
 
-(draw-box "HSXLEN" {:span 32 :borders {}})
-----
+(draw-box "64" {:span 32 :borders {}})
+----

src/priv-csrs.adoc

@@ -438,25 +438,29 @@ Supervisor interrupt pending.
 `0x603` +
 `0x604` +
 `0x606` +
-`0x607` 
+`0x607` +
+`0x612`
 |HRW + 
 HRW +
 HRW +
 HRW +
 HRW +
+HRW +
 HRW 
 |`hstatus` +
 `hedeleg` +
 `hideleg` +  
 `hie` +  
 `hcounteren` + 
-`hgeie`
+`hgeie` +
+`hedelegh`
 |Hypervisor status register. +
 Hypervisor exception delegation register. +
 Hypervisor interrupt delegation register. +
 Hypervisor interrupt-enable register. +
 Hypervisor counter enable. +
-Hypervisor guest external interrupt-enable register.
+Hypervisor guest external interrupt-enable register. +
+Upper 32 bits of `hedeleg`, RV32 only.
 
 4+^|Hypervisor Trap Handling
 
@@ -618,7 +622,7 @@ Machine interrupt-enable register. +
 Machine trap-handler base address. +
 Machine counter enable. +
 Additional machine status register, RV32 only. +
-Additional machine exception delegation register, RV32 only.
+Upper 32 bits of `medeleg`, RV32 only.
 
 4+^|Machine Trap Handling
 

src/priv-preface.adoc

@@ -36,7 +36,7 @@ version 1.12:
 
 * Defined the `misa`.V field to reflect that the V extension has been
 implemented.
-* Defined the RV32-only `medelegh` CSR.
+* Defined the RV32-only `medelegh` and `hedelegh` CSRs.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
 * Clarified semantics of explicit accesses to CSRs wider than XLEN bits.