Clarify meaning of "platform or custom use"

Resolves #1128

src/hypervisor.adoc

@@ -322,7 +322,7 @@ external interrupt (code 9) for VS-mode, including the value written to
 interrupt (6) is translated into a supervisor timer interrupt (5) for
 VS-mode, and a virtual supervisor software interrupt (2) is translated
 into a supervisor software interrupt (1) for VS-mode. Similar
-translations may or may not be done for platform or custom interrupt
+translations may or may not be done for platform interrupt
 causes (codes 16 and above).
 
 [[hedeleg-bits]]
@@ -1761,7 +1761,7 @@ Machine external interrupt
 ≥16
 |Supervisor guest external interrupt +
 _Reserved_ +
-_Designated for platform or custom use_ 
+_Designated for platform use_
 |0 +
 0 +
 0 +

src/machine.adoc

@@ -1227,7 +1227,10 @@ MXLEN-bit read/write register containing interrupt enable bits.
 Interrupt cause number _i_ (as reported in CSR `mcause`,
 <<mcause>>) corresponds with bit _i_ in both `mip` and
 `mie`. Bits 15:0 are allocated to standard interrupt causes only, while
-bits 16 and above are designated for platform or custom use.
+bits 16 and above are designated for platform use.
+
+NOTE: Interrupts designated for platform use may be designated for custom use
+at the platform's discretion.
 
 .Machine Interrupt-Pending Register (mip).
 include::images/bytefield/mideleg.adoc[]

src/priv-preface.adoc

@@ -39,6 +39,8 @@ implemented.
 * Defined the RV32-only `medelegh` and `hedelegh` CSRs.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
+* Clarified that "platform- or custom-use" interrupts are actually
+"platform-use interrupts", where the platform can choose to make some custom.
 * Clarified semantics of explicit accesses to CSRs wider than XLEN bits.
 * Clarified that MXLEN≥SXLEN, and added the constraint that
 SXLEN≥UXLEN.

src/supervisor.adoc

@@ -225,7 +225,7 @@ SXLEN-bit read/write register containing interrupt enable bits.
 Interrupt cause number _i_ (as reported in CSR `scause`,
 <<scause>>) corresponds with bit _i_ in both `sip` and
 `sie`. Bits 15:0 are allocated to standard interrupt causes only, while
-bits 16 and above are designated for platform or custom use.
+bits 16 and above are designated for platform use.
 
 .Supervisor interrupt-pending register (`sip`).
 include::images/bytefield/sip.edn[]