Further clarify behavior of CSR access side effects

src/zicsr.adoc

@@ -52,11 +52,12 @@ write to the CSR at all, and so shall not cause any of the side effects
 that might otherwise occur on a CSR write, nor raise illegal-instruction
 exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always
 read the addressed CSR and cause any read side effects regardless of
-_rs1_ and _rd_ fields. Note that if _rs1_ specifies a register holding a
-zero value other than `x0`, the instruction will still attempt to write
-the unmodified value back to the CSR and will cause any attendant side
-effects. A CSRRW with _rs1_=`x0` will attempt to write zero to the
-destination CSR.
+_rs1_ and _rd_ fields.
+Note that if _rs1_ specifies a register other than `x0`, and that register
+holds a zero value, the instruction will not action any attendant per-field
+side effects, but will action any side effects caused by writing to the entire
+CSR.
+A CSRRW with _rs1_=`x0` will attempt to write zero to the destination CSR.
 
 The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and
 CSRRC respectively, except they update the CSR using an XLEN-bit value
@@ -114,6 +115,8 @@ has at least one bit set corresponding to that field.
 As of this writing, no standard CSRs have side effects on field writes.
 Hence, whether a standard CSR access has any side effects can be determined
 solely from the opcode.
+
+Defining CSRs with side effects on field writes is not recommended.
 ====
 
 For any event or consequence that occurs due to a CSR having a