Merge pull request #1246 from riscv/clarify-sfence-w-inval

Clarify when SFENCE.W.INVAL/SFENCE.INVAL.IR are legal

src/supervisor.adoc

@@ -2021,6 +2021,12 @@ or VU-mode, or to execute SINVAL.VMA in VU-mode, raises a
 virtual-instruction exception. When `hstatus`.VTVM=1, an attempt to execute
 SINVAL.VMA in VS-mode also raises a virtual instruction exception.
 
+Attempting to execute SFENCE.W.INVAL or SFENCE.INVAL.IR in U-mode
+raises an illegal-instruction exception.
+Doing so in VU-mode raises a virtual-instruction exception.
+SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the `mstatus`.TVM and
+`hstatus`.VTVM fields and hence are always permitted in S-mode and VS-mode.
+
 [NOTE]
 ====
 SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be