Integrate Zicfilp and Zicfiss extension specs (#1380)

- Updates CSR, Machine, Supervisor and Hypervisor chapters
 - Adds CFI chapter to Priv. and Unpriv.

src/hypervisor.adoc

@@ -580,7 +580,24 @@ mode V=1.
 
 [[henvcfg]]
 .Hypervisor environment configuration register (`henvcfg`).
-include::images/bytefield/henvcfg.edn[]
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'FIOM'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'LPE'},
+  {bits:  1, name: 'SSE'},
+  {bits:  2, name: 'CBIE'},
+  {bits:  1, name: 'CBCFE'},
+  {bits:  1, name: 'CBZE'},
+  {bits: 24, name: 'WPRI'},
+  {bits:  2, name: 'PMM'},
+  {bits: 27, name: 'WPRI'},
+  {bits:  1, name: 'ADUE'},
+  {bits:  1, name: 'PBMTE'},
+  {bits:  1, name: 'STCE'},
+], config:{lanes: 4, hspace:1024}}
+....
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `henvcfg`,
 FENCE instructions executed when V=1 are modified so the requirement to
@@ -638,6 +655,26 @@ The definition of the PMM field will be furnished by the forthcoming
 Ssnpm extension. Its allocation within `henvcfg` may change prior to the
 ratification of that extension.
 
+The Zicfilp extension adds the `LPE` field in `henvcfg`. When the `LPE` field
+is set to 1, the Zicfilp extension is enabled in VS-mode. When the `LPE` field
+is 0, the Zicfilp extension is not enabled in VS-mode and the following rules
+apply to VS-mode:
+
+* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`.
+* The `LPAD` instruction operates as a no-op.
+
+The Zicfiss extension adds the `SSE` field in `henvcfg`. If the `SSE` field is
+set to 1, the Zicfiss extension is activated in VS-mode. When the `SSE` field is
+0, the Zicfiss extension remains inactive in VS-mode, and the following rules
+apply when `V=1`: 
+
+* 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
+* 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
+* The `pte.xwr=010b` encoding in VS-stage page tables becomes reserved.
+* The `senvcfg.SSE` field will read as zero and is read-only.
+* When `menvcfg.SSE` is one, `SSAMOSWAP.W/D` raises a virtual instruction
+  exception.
+
 When XLEN=32, `henvcfgh` is a
 32-bit read/write register that aliases bits 63:32
 of `henvcfg`. Register `henvcfgh` does not exist when
@@ -894,11 +931,57 @@ normally read or modify `sstatus` actually access `vsstatus` instead.
 
 [[vsstatusreg-rv32]]
 .Virtual supervisor status (`vstatus`) register when VSXLEN=32.
-include::images/bytefield/vsstatusreg-rv32.edn[]
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SIE'},
+  {bits:  3, name: 'WPRI'},
+  {bits:  1, name: 'SPIE'},
+  {bits:  1, name: 'UBE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SPP'},
+  {bits:  2, name: 'VS[1:0]'},
+  {bits:  2, name: 'WPRI'},
+  {bits:  2, name: 'FS[1:0]'},
+  {bits:  2, name: 'XS[1:0]'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SUM'},
+  {bits:  1, name: 'MXR'},
+  {bits:  3, name: 'WPRI'},
+  {bits:  1, name: 'SPELP'},
+  {bits:  7, name: 'WPRI'},
+  {bits:  1, name: 'SD'},
+], config:{lanes: 2, hspace:1024}}
+....
 
 [[vsstatusreg]]
 .Virtual supervisor status (`vsstatus`) register when VSXLEN=64.
-include::images/bytefield/vsstatusreg.edn[]
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SIE'},
+  {bits:  3, name: 'WPRI'},
+  {bits:  1, name: 'SPIE'},
+  {bits:  1, name: 'UBE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SPP'},
+  {bits:  2, name: 'VS[1:0]'},
+  {bits:  2, name: 'WPRI'},
+  {bits:  2, name: 'FS[1:0]'},
+  {bits:  2, name: 'XS[1:0]'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SUM'},
+  {bits:  1, name: 'MXR'},
+  {bits:  3, name: 'WPRI'},
+  {bits:  1, name: 'SPELP'},
+  {bits:  8, name: 'WPRI'},
+  {bits:  2, name: 'UXL[1:0]'},
+  {bits: 29, name: 'WPRI'},
+  {bits:  1, name: 'SD'},
+], config:{lanes: 4, hspace:1024}}
+....
 
 The UXL field controls the effective XLEN for VU-mode, which may differ
 from the XLEN for VS-mode (VSXLEN). When VSXLEN=32, the UXL field does
@@ -945,6 +1028,13 @@ machine, unless a virtual-machine load/store (HLV, HLVX, or HSV) or the
 MPRV feature in the `mstatus` register is used to execute a load or
 store _as though_ V=1.
 
+The Zicfilp extension adds the `SPELP` field that holds the previous `ELP`, and
+is updated as specified in <<ZICFILP_FORWARD_TRAPS>>. The `SPELP` field is
+encoded as follows:
+
+* 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
+* 1 - `LP_EXPECTED` - a landing pad instruction is expected.
+
 ==== Virtual Supervisor Interrupt (`vsip` and `vsie`) Registers 
 
 The `vsip` and `vsie` registers are VSXLEN-bit read/write registers that