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add ssqosid to extensions table (#1707) RISC-V ISA Build #1186: Commit 192eeeb pushed by aswaterman
November 4, 2024 04:29 6m 51s main
main
November 4, 2024 04:29 6m 51s
Add Ssqosid to extensions table in preface RISC-V ISA Build #1185: Pull request #1707 opened by ved-rivos
November 2, 2024 23:30 7m 8s ved-rivos:1102
ved-rivos:1102
November 2, 2024 23:30 7m 8s
Release New ISA When Merging a PR Release New ISA When Merging a PR #232: completed by aswaterman
November 2, 2024 01:26 7m 40s
November 2, 2024 01:26 7m 40s
Release New ISA When Merging a PR Release New ISA When Merging a PR #231: completed by aswaterman
November 2, 2024 01:24 7m 2s
November 2, 2024 01:24 7m 2s
Merge branch 'ved-rivos-1101' RISC-V ISA Build #1184: Commit 6114bf9 pushed by aswaterman
November 2, 2024 01:17 7m 21s main
main
November 2, 2024 01:17 7m 21s
Move Machine/Supervisor to v1.14-draft (#1706) RISC-V ISA Build #1183: Commit 4a428b0 pushed by aswaterman
November 2, 2024 01:15 10m 28s main
main
November 2, 2024 01:15 10m 28s
Move Machine/Supervisor to v1.14-draft RISC-V ISA Build #1182: Pull request #1706 opened by aswaterman
November 2, 2024 01:08 6m 58s priv-1.14-draft
priv-1.14-draft
November 2, 2024 01:08 6m 58s
Integrated Ssqosid extension RISC-V ISA Build #1181: Pull request #1705 opened by ved-rivos
November 1, 2024 13:41 7m 17s ved-rivos:1101
ved-rivos:1101
November 1, 2024 13:41 7m 17s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1180: Pull request #1653 synchronize by nibrunieAtSi5
October 31, 2024 20:06 7m 15s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 31, 2024 20:06 7m 15s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1179: Pull request #1653 synchronize by nibrunieAtSi5
October 31, 2024 16:49 7m 11s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 31, 2024 16:49 7m 11s
Release New ISA When Merging a PR Release New ISA When Merging a PR #230: completed by aswaterman
October 28, 2024 23:39 7m 20s
October 28, 2024 23:39 7m 20s
Fix NOTE about ARM FMA mnemonics (#1700) RISC-V ISA Build #1177: Commit 34b6e75 pushed by aswaterman
October 28, 2024 23:32 7m 1s main
main
October 28, 2024 23:32 7m 1s
Fix NOTE about ARM FMA mnemonics RISC-V ISA Build #1176: Pull request #1700 opened by aswaterman
October 28, 2024 23:25 7m 2s fix-fnmadd-note
fix-fnmadd-note
October 28, 2024 23:25 7m 2s
Release New ISA When Merging a PR Release New ISA When Merging a PR #229: completed by aswaterman
October 28, 2024 22:57 7m 6s
October 28, 2024 22:57 7m 6s
Improve table: Compressed instruction formats (#1696) RISC-V ISA Build #1175: Commit e24a456 pushed by aswaterman
October 28, 2024 22:50 7m 4s main
main
October 28, 2024 22:50 7m 4s
Improve table: Compressed instruction formats RISC-V ISA Build #1172: Pull request #1696 opened by cousteaulecommandant
October 24, 2024 10:47 7m 13s cousteaulecommandant:patch-1
cousteaulecommandant:patch-1
October 24, 2024 10:47 7m 13s
Release New ISA When Merging a PR Release New ISA When Merging a PR #228: completed by wmat
October 22, 2024 04:50 6m 40s
October 22, 2024 04:50 6m 40s
Merge pull request #1694 from james-ball-qualcomm/main RISC-V ISA Build #1171: Commit 084b690 pushed by wmat
October 22, 2024 04:43 7m 6s main
main
October 22, 2024 04:43 7m 6s
Fix for issue 1693 (HSLEN should be HSXLEN) RISC-V ISA Build #1170: Pull request #1694 opened by james-ball-qualcomm
October 22, 2024 04:14 7m 6s james-ball-qualcomm:main
james-ball-qualcomm:main
October 22, 2024 04:14 7m 6s
Release New ISA When Merging a PR Release New ISA When Merging a PR #227: completed by aswaterman
October 19, 2024 00:50 7m 15s
October 19, 2024 00:50 7m 15s
Update unpriv-cfi.adoc from suggestion (#1690) RISC-V ISA Build #1168: Commit ae98787 pushed by aswaterman
October 19, 2024 00:42 7m 11s main
main
October 19, 2024 00:42 7m 11s
[vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL RISC-V ISA Build #1167: Pull request #1653 synchronize by nibrunieAtSi5
October 18, 2024 21:42 7m 12s nibrunieAtSi5:vcrypto-lmul-align-clarification
nibrunieAtSi5:vcrypto-lmul-align-clarification
October 18, 2024 21:42 7m 12s
remove redundant 'rd == x0' RISC-V ISA Build #1166: Pull request #1690 opened by kacouane
October 18, 2024 08:49 7m 8s kacouane:cfi_fix_return_def
kacouane:cfi_fix_return_def
October 18, 2024 08:49 7m 8s
Release New ISA When Merging a PR Release New ISA When Merging a PR #226: completed by aswaterman
October 18, 2024 02:24 7m 7s
October 18, 2024 02:24 7m 7s
priv 1.13 is ratified (#1689) RISC-V ISA Build #1165: Commit 2c07aa2 pushed by aswaterman
October 18, 2024 02:16 7m 1s main
main
October 18, 2024 02:16 7m 1s