Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

fix inconsistencies on xnxti CSR #438

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
+13 −11
Open

fix inconsistencies on xnxti CSR #438

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
24 changes: 13 additions & 11 deletions src/clic.adoc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1004,12 +1004,19 @@ NOTE: Vertical interrupts to higher privilege modes will be taken
preemptively by the hardware, so {mnxti} effectively only ever handles
the next interrupt in the same privilege mode.

Pseudo-code for csrrsi rd, mnxti, uimm[4:0] in M mode:
Pseudo-code for csrrsi|csrrci rd, mnxti, uimm[4:0] in M mode:
[source]
----
// clic.priv, clic.level, clic.id represent the highest-ranked
// interrupt currently present in the CLIC
mstatus |= uimm[4:0]; // Performed regardless of interrupt readiness.
// Performed regardless of interrupt readiness.
if (funct3 == csrrsi) {
mstatus.mie |= uimm[3];
mstatus.sie |= uimm[1];
} else { // csrrci
mstatus.mie &= !uimm[3];
mstatus.sie &= !uimm[1];
}
if (clic.priv==M && clic.level > mcause.mpil && clic.level > mintthresh.th) {
// There is an available interrupt.
if (uimm[4:0] != 0) { // Side-effects should occur.
Expand All @@ -1026,8 +1033,6 @@ Pseudo-code for csrrsi rd, mnxti, uimm[4:0] in M mode:
// No interrupt or in non-CLIC mode.
rd = 0;
}
// When a different CSR instruction is used, the update of mstatus and the test
// for whether side-effects should occur are modified accordingly.
// When a different privileges xnxti CSR is accessed then clic.priv is compared with
// the corresponding privilege and xstatus, xintstatus.xil, xcause.exccode are the
// corresponding privileges CSRs.
Expand All @@ -1037,13 +1042,12 @@ Pseudo-code for csrrs rd, mnxti, rs1 in M mode:
[source]
----
// clic.priv, clic.level, clic.id represent the highest-ranked interrupt currently present in the CLIC
if (rs1 != x0)
{
mstatus |= rs1[4:0]; // Performed regardless of interrupt readiness.
}
// Performed regardless of interrupt readiness.
mstatus.mie |= rs1[3];
mstatus.sie |= rs1[1];
if (clic.priv==M && clic.level > rs1[23:16] && clic.level > mintthresh.th) {
// There is an available interrupt.
if (rs1[4:0] != 0 && rs1 != x0) { // Side-effects should occur.
if (rs1 != x0) { // Side-effects should occur.
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This changes can t be accepted since it is changing the initial behavior.

Currently I m starting a thread of mail with ARC to better understand what we should do.

Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you for your response.

This changes can t be accepted since it is changing the initial behavior.

This PR does not propose a change to the specifications.

We have to change either the pseudo code or the following descriptions.

If the CSR instruction that accesses mnxti includes a write, ...

Following the usual convention for CSR instructions, if the CSR instruction does not include write side effects (e.g., csrr t0, mnxti), then no state update on any CSR occurs.

Currently I m starting a thread of mail with ARC to better understand what we should do.

Thank you!

On the other hand, #399, I opened last July, requires changing the behavior. The current specification simply does not work (If I understand correctly).

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

A thread of mail has been started to understand the best way to proceed with NXTI.
I ll keep you updated

// Commit to servicing the available interrupt.
mintstatus.mil = clic.level; // Update hart's interrupt level.
mcause.exccode = clic.id; // Update interrupt id in mcause.
Expand All @@ -1058,8 +1062,6 @@ Pseudo-code for csrrs rd, mnxti, rs1 in M mode:
rd = 0;
}

// When a different CSR instruction is used, the update of mstatus and the test
// for whether side-effects should occur are modified accordingly.
// When a different privileges mnxti CSR is accessed then clic.priv is compared with
// the corresponding privilege and mstatus, mintstatus.mil, mcause.exccode are the
// corresponding privileges CSRs.
Expand Down