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Prototype DTS entry #91
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I think this would be useful as an appendix, though not part of normative text. The primary parameters are the base address of the memory apertures and the number and routing of the interrupts. |
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attempt at a DTS entry for CLIC. For issue riscv#91
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recreating a pull because pull riscv#130 had merge issues.
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attempt at a DTS entry for CLIC for issue #91
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changes since last pdf update listed below: 04/22/2021 updated adoc format to align with risc-v template, added revision history 04/18/2021 Added Bibliography section 04/15/2021 issue #45 - for rev1.0 mtvec not xtvec controls enabling CLIC mode for all priv 04/13/2021 issue #141 - N-extension vs Bare S-mode note added. 04/13/2021 issue #117,#125 fix - change text to match table in M/S/U system if nmbits==1 04/12/2021 issue #47 fix - add CLIC reset behavior section 04/12/2021 issue #26 fix - modify wording that defined micro-architectural behavior of xINHV 04/12/2021 issue #91 - add DTS entry example 04/12/2021 added CLIC comparision to Advance Interupt Architecture (AIA) 04/12/2021 issue #111,#105 fix - For hardware vectoring access exceptions, both {tval} and {epc} holds the faulting address 04/08/2021 issue #49, #79 - downplay M/S/U memory map requirements 03/30/2021 issue #29 - updated memory map table reserved section to give room for clicinttrig 03/30/2021 issue #122 fix - remove wording referring to register
AIA and PLIC specs do not contain DTS entries. However, Spike model does. appending this DTS entry issue spike issue #242 |
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Should the spec contain a prototypical DTS entry?
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