Clarify Memory Access acts like data access. #1065
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Yes. The Zifencei chapter of the unpriv spec says: "RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on a RISC-V hart until that hart executes a FENCE.I instruction." |
There was a problem hiding this comment.
I would say something more like "This command lets the debugger perform memory accesses, with the exact same memory view and permissions as performing a load/store on the selected hart." Then that leads nicely into the next sentence about memory-mapped registers.
I'm not sure if this is necessary. Does RISC-V allow data loads to differ from instruction fetches? For a long time any mention of caches was avoided in all specs. Inspired by #1062.
rtwfroody
force-pushed
the
memory_access
branch
from
a9081aa
to
6e44fd5
Compare
|
@pdonahue-ventana sounds good. Changed. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
I'm not sure if this is necessary. Does RISC-V allow data loads to differ from instruction fetches? For a long time any mention of caches was avoided in all specs.
Inspired by #1062.