v0.8.1-scalar

Decisions Taken:

• Following feedback (#65) and discussion at the Dec 17th 2020 TG meeting, the encoding scheme for the SM4 and RV32 AES instructions has been updated.

Changes:

• Changed how the SM4 and RV32 instructions are encoded.
  • Formerly, we required rd==rs1 to reclaim some encoding space, given that these instructions are designed to be used this way.
  • Now, we require implementations to source rd from the rs1 field, and the rd field is now re-used as normal encoding space.
  • We hope this paves the way for a more standardised "destructive" encoding format for RISC-V.
  • More rationale for this decision is found in Appendix A.1 of the specification.
  • Binutils, Spike, SAIL and the benchmarks have been updated to reflect this change. This includes a small assembly syntax change:
    • aes* rd, rs1, rs2, bs is now aes* rt, rs2, bs.
    • sm4* rd, rs1, rs2, bs is now sm4* rt, rs2, bs.
• Updated the Entropy Source diagram (See bcdcb31).

Additions:

• None

Removals:

• None

Open Issues:

See the status of the open issues in the project board.