encodings: Add rs1==rd restriction to sm4ed/sm4ks

 On branch dev/next-release
 Your branch is up-to-date with 'origin/dev/next-release'.

 Changes to be committed:
	modified:   doc/opcodes-crypto-scalar-cmds.tex
	modified:   tools/opcodes-crypto-scalar-both

 Changes not staged for commit:
	modified:   extern/riscv-compliance (modified content)
	modified:   extern/riscv-gnu-toolchain (modified content, untracked content)
	modified:   extern/riscv-isa-sim (modified content)
	modified:   extern/sail-riscv (modified content, untracked content)

doc/opcodes-crypto-scalar-cmds.tex

@@ -18,7 +18,7 @@
 \bitbox{2}{\tt bs}
 \bitbox{5}{\tt 11000}
 \bitbox{5}{\tt rs2}
-\bitbox{5}{\tt rs1}
+\bitbox{5}{\tt rs1==rd}
 \bitbox{3}{\tt 000}
 \bitbox{5}{\tt rd}
 \bitbox{7}{\tt 0110011}
@@ -28,7 +28,7 @@
 \bitbox{2}{\tt bs}
 \bitbox{5}{\tt 11010}
 \bitbox{5}{\tt rs2}
-\bitbox{5}{\tt rs1}
+\bitbox{5}{\tt rs1==rd}
 \bitbox{3}{\tt 000}
 \bitbox{5}{\tt rd}
 \bitbox{7}{\tt 0110011}

tools/opcodes-crypto-scalar-both

@@ -10,8 +10,8 @@
 @getnoise     rd 19..15=0 31..20=0x7A9 14..12=0 6..0=0b1110011
 
 # Scalar SM4 - RV32, RV64
-sm4ed         rd rs1 rs2 bs   29..25=0b11000                14..12=0 6..0=0x33
-sm4ks         rd rs1 rs2 bs   29..25=0b11010                14..12=0 6..0=0x33
+sm4ed         rd rs1 rs2 bs rs1:==rd 29..25=0b11000 14..12=0 6..0=0x33
+sm4ks         rd rs1 rs2 bs rs1:==rd 29..25=0b11010 14..12=0 6..0=0x33
 
 # Scalar SM3 - RV32, RV64
 sm3p0         rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13