fix indentation

cfi_backward.adoc

@@ -49,11 +49,11 @@ the `c.mop.0`, `c.mop.1` and `c.mop.2` encodings defined by the Zcmop extension.
 When a Zimop encoding is not used by the Zicfiss extension then the
 instruction follows its Zimop defined behavior.
 
-== Zicfiss CSRs
+=== Zicfiss CSRs
 
 This chapter specifies the CSR state of the Zicfiss extensions.
 
-=== Machine environment configuration registers (`menvcfg and menvcfgh`)
+==== Machine environment configuration registers (`menvcfg and menvcfgh`)
 
 .Machine environment configuration register (`menvcfg`) for MXLEN=64
 [wavedrom, ,svg]
@@ -83,7 +83,7 @@ rules apply to privilege modes less than M.
 * The `pte.xwr=010b` encoding in S-stage page tables is reserved.
 * The `henvcfg.SSE` and `senvcfg.SSE` fields are read-only zero.
 
-=== Supervisor environment configuration registers (`senvcfg`)
+==== Supervisor environment configuration registers (`senvcfg`)
 
 .Supervisor environment configuration register (`senvcfg`)
 [wavedrom, ,svg]
@@ -107,7 +107,7 @@ rules apply:
 * The 32-bit Zicfiss instructions revert to their Zimop defined behavior.
 * The 16-bit Zicfiss instructions revert to their Zcmop defined behavior.
 
-=== Hypervisor environment configuration registers (`henvcfg and henvcfgh`)
+==== Hypervisor environment configuration registers (`henvcfg and henvcfgh`)
 
 .Hypervisor environment configuration register (`henvcfg`) for MXLEN=64
 [wavedrom, ,svg]
@@ -137,15 +137,15 @@ rules apply when `V=1`.
 * The `pte.xwr=010b` encoding in VS-stage page tables is reserved.
 * The `senvcfg.SSE` field is read-only zero.
 
-=== Shadow stack pointer (`ssp`)
+==== Shadow stack pointer (`ssp`)
 
 The `ssp` CSR is an unprivileged read-write (URW) CSR that reads and writes `XLEN`
 low order bits of the shadow stack pointer (`ssp`). There is no high CSR defined
 as the `ssp` is always as wide as the `XLEN` of the current privilege mode. The
 bits 1:0 of `ssp` are read-only zero. If the UXLEN or SXLEN may never be 32,
 then the bit 2 is also read-only zero.
 
-=== Machine Security Configuration (`mseccfg`)
+==== Machine Security Configuration (`mseccfg`)
 
 .Machine security configuration register (`mseccfg`) when `MXLEN=64`
 [wavedrom, ,svg]

cfi_forward.adoc

@@ -103,11 +103,11 @@ not a valid landing pad or may use an alternate register allocation to prevent
 the accidental landing pad.
 ====
 
-== Zicfilp CSRs
+=== Zicfilp CSRs
 
 This chapter specifies the CSR state of the Zicfilp extension.
 
-=== Machine environment configuration registers (`menvcfg and menvcfgh`)
+==== Machine environment configuration registers (`menvcfg and menvcfgh`)
 
 .Machine environment configuration register (`menvcfg`) for MXLEN=64
 [wavedrom, ,svg]
@@ -136,7 +136,7 @@ rules apply to S-mode:
   state is always `NO_LP_EXPECTED`.
 * The `lpad` instruction executes as a no-op.
 
-=== Supervisor environment configuration registers (`senvcfg`)
+==== Supervisor environment configuration registers (`senvcfg`)
 
 .Supervisor environment configuration register (`senvcfg`)
 [wavedrom, ,svg]
@@ -161,7 +161,7 @@ following rules apply to VU/U-mode:
   state is always `NO_LP_EXPECTED`.
 * The `lpad` instruction executes as a no-op.
 
-=== Hypervisor environment configuration registers (`henvcfg and henvcfgh`)
+==== Hypervisor environment configuration registers (`henvcfg and henvcfgh`)
 
 .Hypervisor environment configuration register (`henvcfg`) for MXLEN=64
 [wavedrom, ,svg]
@@ -190,7 +190,7 @@ rules apply to VS-mode:
   state is always `NO_LP_EXPECTED`.
 * The `lpad` instruction executes as a no-op.
 
-=== Machine status registers (`mstatus`)
+==== Machine status registers (`mstatus`)
 
 .Machine-mode status register (`mstatus`) for RV64
 [wavedrom, ,svg]
@@ -235,7 +235,7 @@ fields that hold the previous `ELP`, and are updated as specified in
 * 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
 * 1 - `LP_EXPECTED` - a landing pad instruction is expected.
 
-=== Supervisor status registers (`sstatus`)
+==== Supervisor status registers (`sstatus`)
 
 .Supervisor-mode status register (`sstatus`) when `SXLEN=64`
 [wavedrom, ,svg]
@@ -268,7 +268,7 @@ Access to the `SPELP` field introducecd by Zicfilp accesses the homonymous
 fields of `mstatus` when `V=0` and the homonymous fields of `vsstatus`
 when `V=1`.
 
-=== Virtual supervisor status registers (`vsstatus`)
+==== Virtual supervisor status registers (`vsstatus`)
 
 .Virtual supervisor status register (`vsstatus`) when `VSXLEN=64`
 [wavedrom, ,svg]
@@ -304,7 +304,7 @@ The `SPELP` field is encoded as follows:
 * 0 - `NO_LP_EXPECTED` - no landing pad instruction expected.
 * 1 - `LP_EXPECTED` - a landing pad instruction is expected.
 
-=== Machine Security Configuration (`mseccfg`)
+==== Machine Security Configuration (`mseccfg`)
 
 .Machine security configuration register (`mseccfg`) when `MXLEN=64`
 [wavedrom, ,svg]
@@ -330,7 +330,7 @@ apply to M-mode.
   state is always `NO_LP_EXPECTED`.
 * The `lpad` instruction executes as a no-op.
 
-=== Debug Control and Status (`dcsr`)
+==== Debug Control and Status (`dcsr`)
 
 .Debug Control and Status (`dcsr`)
 [wavedrom, ,svg]