Bump ext/riscv-isa-manual from 084b690 to 7b6911f
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Bumps [ext/riscv-isa-manual](https://github.com/riscv/riscv-isa-manual) from `084b690` to `7b6911f`. - [Release notes](https://github.com/riscv/riscv-isa-manual/releases) - [Commits](riscv/riscv-isa-manual@084b690...7b6911f) --- updated-dependencies: - dependency-name: ext/riscv-isa-manual dependency-version: 7b6911f56fa600358a1202f9d6c1d43f7a45c299 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
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ThinkOpenly
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Superseded by #714. |
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Bumps ext/riscv-isa-manual from
084b690to7b6911f.Commits
7b6911fAdd note about tvec/jvt register layout/alignment (#1988)a7713b9Clarify <nf> in asm syntax equals NFIELDS (#1986)5308687Merge pull request #1980 from jaimiejellema/maina04916eTypographical fixes to xperm and packw instruction listinge5078e5Three minor documentation tweaks (#1974)567502bFix a broken extension reference. (#1968)505d955hypervisor: add HUPMM to hstatus (#1967)d83114cClarify that vaadd intermediate results aren't truncated (#1960)0e940b0Add missing SSE bit in senvcfg for RV32 (#1965)8696121Remove [5:4] after spimm in cm.push/pop wavedrom and assembly syntax explanat...Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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