Add H csr vsip,hgeie,hideleg,hie,hip,hvip,vsie,vsscratch,hgeip

arch/csr/H/hgeie.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeie
+long_name: Hypervisor Guest External Interrupt Enable Register
+description: |
+  The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. Guest external interrupt number i corresponds with bit i in hgeie.
+
+  Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
+
+  [Note]
+  Support for guest external interrupts requires an interrupt controller that can collect virtual-machine-directed interrupts separately from other interrupts.
+
+  The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros.
+
+  Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN.
+address: 0x607
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  GEI_ENABLE:
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type: RW
+    reset_value: 0
+    description: |
+      The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in  hgeie.
+      Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN.

arch/csr/H/hgeip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeip
+long_name: Hypervisor Guest External Interrupt Pending Register
+description: |
+  The hgeip register is an HSXLEN-bit read-only register, formatted as that indicates pending guest external interrupts for this hart.
+
+  Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.
+  If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
+  Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller. To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.
+
+  The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero.
+  This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie
+address: 0xE12
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  GEI_PENDING:
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type: RO
+    reset_value: 0
+    description: |
+      Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller.
+      To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.
+
+      The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN.
+      The least-significant bits are implemented first, apart from bit 0.
+      Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie.

arch/csr/H/hideleg.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hideleg
+long_name: Hypervisor Interrupt Delegation Register
+description: |
+  Register hideleg is an HSXLEN-bit read/write register. By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the medeleg and mideleg CSRs to delegate some traps to HS-mode.
+  The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as medeleg and mideleg.
+  An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set.
+  Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.
+address: 0x603
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SSI:
+    location: 1
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Software Interrupt
+    description: Supervisor Software Interrupt
+
+  VSSI:
+    location: 2
+    type: RW
+    reset_value: 0
+    long_name: Virtual Supervisor Software Interrupt
+    description: Virtual Supervisor Software Interrupt
+
+  STI:
+    location: 5
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Timer Interrupt
+    description: Supervisor Timer Interrupt
+
+  VSTI:
+    location: 6
+    type: RW
+    reset_value: 0
+    long_name: Virtual Supervisor Timer Interrupt
+    description: Virtual Supervisor Timer Interrupt
+
+  SEI:
+    location: 9
+    type: RO
+    reset_value: 0
+    long_name: Supervisor External Interrupt
+    description: Supervisor External Interrupt
+
+  VSEI:
+    location: 10
+    type: RW
+    reset_value: 0
+    long_name: Virtual Supervisor External Interrupt
+    description: Virtual Supervisor External Interrupt
+
+  SGEI:
+    location: 12
+    type: RW
+    reset_value: 0
+    long_name: Supervisor Guest External Interrupt
+    description: Supervisor Guest External Interrupt

arch/csr/H/hie.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hie
+long_name: Hypervisor Interrupt Enable Register
+description: |
+  The `hie` register is a read/write register in HS-mode that enables interrupts.
+  It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements
+  the HS-level `sie` register.
+address: 0x604
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SGEIE:
+    location: 12
+    type: RW-H
+    reset_value: 0
+    description: |
+      Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered
+      to VS-mode based on the `hgeie` setting.
+
+  VSEIE:
+    location: 10
+    type: RW-H
+    reset_value: 0
+    description: |
+      VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level
+      to be processed based on the configuration in `hvip` and other platform-specific sources.
+
+  VSTIE:
+    location: 6
+    type: RW-H
+    reset_value: 0
+    description: |
+      VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed
+      based on the `hvip` configuration and any platform-specific timer interrupts.
+
+  VSSIE:
+    location: 2
+    type: RW-H
+    reset_value: 0
+    description: |
+      VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level
+      to be processed, based on the configuration in `hvip`.

arch/csr/H/hip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hip
+long_name: Hypervisor Interrupt Pending Register
+description: |
+  The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level.
+  It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.
+address: 0x608
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SGEIP:
+    location: 12
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for supervisor guest external interrupts (SGEI).
+      This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero.
+
+  VSEIP:
+    location: 10
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts (VSEI).
+      This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`,
+      and any other external interrupt signal directed to VS-level.
+
+  VSTIP:
+    location: 6
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts (VSTI).
+      This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level.
+
+  VSSIP:
+    location: 2
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level software interrupts (VSSI).
+      This bit is an alias of the `vssip` bit in `hvip`.

arch/csr/H/hvip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hvip
+long_name: Hypervisor Virtual Interrupt Pending Register
+description: |
+  The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.
+  It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.
+address: 0x645
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  VSEIP:
+    location: 10
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts. This bit is writable and
+      is set to 1 to assert a VS-level external interrupt.
+
+  VSTIP:
+    location: 6
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts. This bit is writable and
+      is set to 1 to assert a VS-level timer interrupt.
+
+  VSSIP:
+    location: 2
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level software interrupts. This bit is writable and
+      is set to 1 to assert a VS-level software interrupt.

arch/csr/H/vsie.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsie
+address: 0x204
+virtual_address: 0x144
+long_name: Virtual Supervisor Interrupt Enable
+description: |
+  The vsie register is a VSXLEN-bit read/write register that is VS-mode’s version of
+  supervisor CSR sie. When V=1, vsie substitutes for the usual sie, so instructions that
+  normally read or modify sie actually access vsie instead. However, interrupts directed to
+  HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1.
+
+  When bit 13 of hideleg is zero, vsie.LCOFIE is read-only zero. Else, vsie.LCOFIE is an alias of sie.LCOFIE.
+  When bit 10 of hideleg is zero, vsie.SEIE is read-only zero. Else, vsie.SEIE is an alias of hie.VSEIE.
+  When bit 6 of hideleg is zero, vsie.STIE is read-only zero. Else, vsie.STIE is an alias of hie.VSTIE.
+  When bit 2 of hideleg is zero, vsie.SSIE is read-only zero. Else, vsie.SSIE is an alias of hie.VSSIE.
+priv_mode: VS
+definedBy: H
+length: VSXLEN
+fields:
+  SSIE:
+    location: 1
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hie.VSSIE[0]
+    description: |
+      SSIE. Read-only zero when hideleg[2] is 0. Else, alias of hie.VSSIE.
+
+  STIE:
+    location: 5
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hie.VSTIE[0]
+    description: |
+      STIE. Read-only zero when hideleg[6] is 0. Else, alias of hie.VSTIE.
+
+  SEIE:
+    location: 9
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hie.VSEIE[0]
+    description: |
+      SEIE. Read-only zero when hideleg[10] is 0. Else, alias of hie.VSEIE.
+
+  LCOFIE:
+    location: 13
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: sie.LCOFIE[0]
+    description: |
+      LCOFIE. Read-only zero when hideleg[13] is 0. Else, alias of sie.LCOFIE.

arch/csr/H/vsip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsip
+address: 0x244
+virtual_address: 0x144
+long_name: Virtual Supervisor Interrupt Pending
+description: |
+  The `vsip` register is a VSXLEN-bit read/write register that is VS-mode’s version of the `sip` CSR.
+  When V=1, instructions that normally access `sip` instead access `vsip`. It holds the pending
+  interrupt status for supervisor-level traps in a virtualized environment.
+
+  However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register,
+  not in `vsip`, when V=1.
+
+  The standard portion (bits 15:0) includes individual interrupt-pending bits.
+priv_mode: VS
+definedBy: H
+length: VSXLEN
+fields:
+  SSIP:
+    location: 1
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hip.VSSIP[0]
+    description: |
+      *Supervisor Software Interrupt Pending*
+
+      Indicates a pending software interrupt at the supervisor level.
+      Read-only zero when `hideleg[2] == 0`, else aliased to `hip.VSSIP[0]`.
+
+  STIP:
+    location: 5
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hip.VSTIP[0]
+    description: |
+      *Supervisor Timer Interrupt Pending*
+
+      Indicates a pending timer interrupt at the supervisor level.
+      Read-only zero when `hideleg[6] == 0`, else aliased to `hip.VSTIP[0]`.
+
+  SEIP:
+    location: 9
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: hip.VSEIP[0]
+    description: |
+      *Supervisor External Interrupt Pending*
+
+      Indicates a pending external interrupt at the supervisor level.
+      Read-only zero when `hideleg[10] == 0`, else aliased to `hip.VSEIP[0]`.
+
+  LCOFIP:
+    location: 13
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    alias: sip.LCOFIP[0]
+    description: |
+      *Local Counter Overflow Interrupt Pending*
+
+      Indicates an overflow of a local counter.
+      Read-only zero when `hideleg[13] == 0`, else aliased to `sip.LCOFIP[0]`.

arch/csr/H/vsscratch.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vsscratch
+address: 0x240
+virtual_address: 0x140
+long_name: Virtual Supervisor Scratch Register
+description: |
+  The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of
+  supervisor register sscratch. When V=1, vsscratch substitutes for the usual sscratch,
+  so instructions that normally read or modify sscratch actually access vsscratch instead.
+  The contents of vsscratch never directly affect the behavior of the machine.
+priv_mode: VS
+length: VSXLEN
+definedBy: H
+fields: {}