Add H csr vsip,hgeie,hideleg,hie,hip,hvip,vsie,vsscratch,hgeip

arch/csr/H/hgeie.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeie
+long_name: Hypervisor Guest External Interrupt Enable Register
+description:
+  - id: csr-hgeie-purpose
+    normative: true
+    text: |
+      The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart.
+  - id: csr-hgeie-bits
+    normative: true
+    text: Guest external interrupt number i corresponds with bit i in hgeie.
+  - id: csr-hgeie-interrupts
+    normative: true
+    text: |
+      Guest external interrupts represent interrupts directed to individual virtual machines
+      at VS-level.
+      If a RISC-V platform supports placing a physical device under the direct control of a
+      guest OS with minimal hypervisor intervention (known as pass-through or direct assignment
+      between a virtual machine and the physical device), then, in such circumstance,
+      interrupts from the device are intended for a specific virtual machine.
+  - id: csr-hgeie-controller-req
+    normative: false
+    text: |
+      Support for guest external interrupts requires an interrupt controller that can collect
+      virtual-machine-directed interrupts separately from other interrupts.
+  - id: csr-hgeie-geilen
+    normative: true
+    text: |
+      The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and
+      may be zero.
+      This number is known as `GEILEN`.
+  - id: csr-hgeie-bitorder
+    normative: true
+    text: |
+      The least-significant bits are implemented first, apart from bit 0.
+  - id: csr-hgeie-nonzero-geilen
+    normative: true
+    text: |
+      Hence, if GEILEN is nonzero, bits `GEILEN`:1 shall be writable in hgeie, and all other
+      bit positions shall be read-only zeros.
+  - id: csr-hgeie-select
+    normative: true
+    text: |
+      Register hgeie selects the subset of guest external interrupts that cause a
+      supervisor-level (HS-level) guest external interrupt.
+  - id: csr-hgeie-hgeip
+    normative: true
+    text: |
+      The enable bits in hgeie do not affect the VS-level external interrupt signal selected
+      from hgeip by hstatus.VGEIN.address: 0x607
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  GEI_ENABLE:
+    long_name: Guest external interrupt enable bits
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type(): |
+      return NUM_EXTERNAL_GUEST_INTERRUPTS > 0 ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      return ((MXLEN'1 << NUM_EXTERNAL_GUEST_INTERRUPTS) - 1) & csr_value.GEI_ENABLE;
+    description: |
+      Enable bits; see description of hgeie

arch/csr/H/hgeip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeip
+long_name: Hypervisor Guest External Interrupt Pending Register
+description:
+  - id: csr-hgeip-purpose
+    normative: true
+    text: |
+      The hgeip register is an HSXLEN-bit read-only register that indicates pending guest external interrupts for this hart.
+
+  - id: csr-hgeip-interrupts
+    normative: true
+    text: |
+      Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.
+
+  - id: csr-hgeip-pass-through
+    normative: true
+    text: |
+      If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
+
+  - id: csr-hgeip-summary
+    normative: true
+    text: |
+      Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller.
+
+  - id: csr-hgeip-controller-query
+    normative: true
+    text: |
+      To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.
+
+  - id: csr-hgeip-geilen
+    normative: true
+    text: |
+      The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as `GEILEN`.
+
+  - id: csr-hgeip-bitorder
+    normative: true
+    text: |
+      The least-significant bits are implemented first, apart from bit 0.
+
+  - id: csr-hgeip-readonly-bits
+    normative: true
+    text: |
+      Hence, if GEILEN is nonzero, bits `GEILEN`:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie.
+address: 0xE12
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  GEI_PENDING:
+    long_name: Guest External Interrupts Pending
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending bits; see description of hgeip

arch/csr/H/hideleg.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hideleg
+long_name: Hypervisor Interrupt Delegation Register
+description:
+  - id: csr-hideleg-purpose
+    normative: true
+    text: |
+      Register hideleg is an HSXLEN-bit read/write register. By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the medeleg and mideleg CSRs to delegate some traps to HS-mode.
+
+  - id: csr-hideleg-delegation-to-vs
+    normative: true
+    text: |
+      The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as medeleg and mideleg.
+
+  - id: csr-hideleg-interrupt-forwarding
+    normative: true
+    text: |
+      An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set.
+
+  - id: csr-hideleg-bit-accessibility
+    normative: true
+    text: |
+      Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.
+address: 0x603
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SSI:
+    location: 1
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Software Interrupt
+    description: Supervisor Software Interrupt
+
+  VSSI:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor Software Interrupt
+    description: Delegates the Virtual Supervisor Software Interrupt to VS-mode
+
+  STI:
+    location: 5
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Timer Interrupt
+    description: Supervisor Timer Interrupt
+
+  VSTI:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor Timer Interrupt
+    description: Delegates the Virtual Supervisor Timer Interrupt to VS-mode
+
+  SEI:
+    location: 9
+    type: RO
+    reset_value: 0
+    long_name: Supervisor External Interrupt
+    description: Supervisor External Interrupt
+
+  VSEI:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor External Interrupt
+    description: Delegates the Virtual Supervisor External Interrupt to VS-mode
+
+  SGEI:
+    location: 12
+    type: RW
+    reset_value: 0
+    long_name: Supervisor Guest External Interrupt
+    description: Supervisor Guest External Interrupt
+
+  LCOFI:
+    location: 13
+    definedBy: Sscofpmf
+    long_name: Local Counter Overflow Interrupt
+    description: Delegate Local Counter Overflow Interrupts to VS-mode.
+    type(): |
+      return HIDELEG_LCOFI_MUTABLE ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return HIDELEG_LCOFI_MUTABLE ? UNDEFINED_LEGAL : 0;

arch/csr/H/hie.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hie
+long_name: Hypervisor Interrupt Enable Register
+description:
+  - id: csr-hie-purpose
+    normative: true
+    text: |
+      The `hie` register is a read/write register in HS-mode that enables interrupts.
+      It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements
+      the HS-level `sie` register.
+address: 0x604
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SGEIE:
+    location: 12
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered
+      to VS-mode based on the `hgeie` setting.
+
+  VSEIE:
+    location: 10
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level
+      to be processed based on the configuration in `hvip` and other platform-specific sources.
+
+  VSTIE:
+    location: 6
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed
+      based on the `hvip` configuration and any platform-specific timer interrupts.
+
+  VSSIE:
+    location: 2
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level
+      to be processed, based on the configuration in `hvip`.
+
+  LCOFIE:
+    location: 13
+    definedBy: Sscofpmf
+    long_name: Local Counter Overflow Interrupt Enable
+    description: |
+      Enable Local Counter Overflow Interrupts in VS-mode.
+    type(): |
+      return HIE_LCOFIE_MUTABLE ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return HIE_LCOFIE_MUTABLE ? UNDEFINED_LEGAL : 0;

arch/csr/H/hip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hip
+long_name: Hypervisor Interrupt Pending Register
+description:
+  - id: csr-hip-purpose
+    normative: true
+    text: |
+      The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level.
+      It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.
+address: 0x608
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  SGEIP:
+    location: 12
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for supervisor guest external interrupts (SGEI).
+      This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero.
+
+  VSEIP:
+    location: 10
+    type: RO
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts (VSEI).
+      This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`,
+      and any other external interrupt signal directed to VS-level.
+
+  VSTIP:
+    location: 6
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts (VSTI).
+      This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level.
+
+  VSSIP:
+    location: 2
+    alias: hvip.VSSIP
+    sw_write(csr_value): CSR[hvip].VSSIP = csr_value.VSSIP;
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level software interrupts (VSSI).
+      This bit is an alias of the `vssip` bit in `hvip`.
+
+  LCOFI:
+    location: 13
+    definedBy: Sscofpmf
+    long_name: Local Counter Overflow Interrupt
+    description: Delegate Local Counter Overflow Interrupts to VS-mode.
+    type(): |
+      return HIDELEG_LCOFI_MUTABLE ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value(): |
+      return HIDELEG_LCOFI_MUTABLE ? UNDEFINED_LEGAL : 0;

arch/csr/H/hvip.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hvip
+long_name: Hypervisor Virtual Interrupt Pending Register
+description:
+  - id: csr-hvip-purpose
+    normative: true
+    text: |
+      The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.
+      It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.
+address: 0x645
+priv_mode: S
+definedBy: H
+length: SXLEN
+fields:
+  VSEIP:
+    location: 10
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts. This bit is writable and
+      is set to 1 to assert a VS-level external interrupt.
+
+  VSTIP:
+    location: 6
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts. This bit is writable and
+      is set to 1 to assert a VS-level timer interrupt.
+
+  VSSIP:
+    location: 2
+    type: RW
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level software interrupts. This bit is writable and
+      is set to 1 to assert a VS-level software interrupt.