Add DCSR and DPC CSRs

[neverlandiz]

This PR addresses Issue #570 and adds the remaining missing debug CSRs

• DCSR
• DPC

[neverlandiz]

For core debug registers like DCSR and DPC, it’s stated that “these registers are only accessible from Debug Mode” (Section 4.9, debug specs). What would be the correct priv_mode for those CSRs? Debug mode isn’t one of the options in the schema (only M, S, U, VS).

[ThinkOpenly]

For core debug registers like DCSR and DPC, it’s stated that “these registers are only accessible from Debug Mode” (Section 4.9, debug specs). What would be the correct priv_mode for those CSRs? Debug mode isn’t one of the options in the schema (only M, S, U, VS).

Hmm. The Priv spec 1.3 "Debug Mode" says:

Debug mode (D-mode) can be considered an additional privilege mode, with even more access than M-mode.

That sounds like a full Mode (capital M). It probably needs to be treated as such, adding a new mode in schemas/csr_schema.json, and an entry in arch/isa/globals.isa, but there don't appear to be any CSR bits to identify "D-mode" (I couldn't find any). So, which new enum value to choose is an open question. Maybe @dhower-qc has an idea?

Some additional information: arch/isa/globals.isa has:

# encoded as defined in the privilege spec
enum PrivilegeMode {
  M  0b011
  S  0b001
  HS 0b001 # alias for S when H extension is used
  U  0b000
  VS 0b101
  VU 0b100
}

These 3 bits appear to be the concatenation of MPV and MPP, or at least they line up that way in the Priv spec, 18.4.1 "Machine Status Registers (mstatus and mstatush)", table 32:

It may be that you could just pick a random new enum value (prepend a 4th bit, like 0b1000?), but I don't know for sure. (You could certainly try!)

[dhower-qc]

Yea, we do need to add D-mode in globals.isa, and yes, there are cases where we are relying on the encoding of PrivilegeMode being the table Paul added above. For example:

riscv-unified-db/arch/isa/globals.isa

Lines 628 to 634 in 00f1540

	$pc = {CSR[stvec].BASE, 2'b00};
	CSR[scause].INT = 1'b0;
	CSR[scause].CODE = $bits(code);
	CSR[hstatus].GVA = 1;
	CSR[hstatus].SPV = 1; # guest page faults always come from a virtual mode
	CSR[hstatus].SPVP = $bits(from_mode)[0];
	CSR[mstatus].SPP = $bits(from_mode)[0];

As such, we should encode D as 0b1011 since it is M (0b0011) with extra permission.