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Vector arith idl #605
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Vector arith idl #605
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…the spec. This is required for several use cases like Go risc-v support which relies only on 64-bit spec, thus being able to filter rv32 CSRs is mandatory. (riscv-software-src#532) Signed-off-by: Afonso Oliveira <[email protected]> Co-authored-by: Derek Hower <[email protected]>
Co-authored-by: Your Name <[email protected]> Co-authored-by: Derek Hower <[email protected]>
…nt extension (riscv-software-src#543) Signed-off-by: Albert Yosher <[email protected]>
* Separate Zcf and Zcd extensions from Zce Signed-off-by: Albert Yosher <[email protected]> * Restore per-instruction dependencies of Zcf/Zcd Signed-off-by: Albert Yosher <[email protected]> --------- Signed-off-by: Albert Yosher <[email protected]>
…rc#551) * Xqci/Xqcibm extension: fix some representation issues, fix qc.extdur rs1 != 31 Signed-off-by: Albert Yosher <[email protected]> * Xqci: fix asciidoc formatting in description * gen:adoc fix asciidoc generation of IDL csr read * gen:ext_pdf fix implication list; improve version display * Add missing word 'CSRs' in CSR summary generation Signed-off-by: Albert Yosher <[email protected]> --------- Signed-off-by: Albert Yosher <[email protected]> Co-authored-by: Albert Yosher <[email protected]>
* Add initial Golang generation support. Signed-off-by: Afonso Oliveira <[email protected]> * Enhance go generator to allow filtering by extensions * Enhance Go CSR generation by filtering out unused extensions and define set of extensions that GO currently supports. Signed-off-by: Afonso Oliveira <[email protected]> * update checked out version of inst.go changed by latest commits. Signed-off-by: Afonso Oliveira <[email protected]> * Refactor to ensure reusable code, given the extensibility of outputs generator.py may be used to generate. Signed-off-by: Afonso Oliveira <[email protected]> * Fix Go awkward struct spacing. Signed-off-by: Afonso Oliveira <[email protected]> * Add rake task to generate Golang input - inst.go Signed-off-by: Afonso Oliveira <[email protected]> * Add CSR ordering to match riscv-opcodes. Signed-off-by: Afonso Oliveira <[email protected]> * Remove checked out inst.go Signed-off-by: Afonso Oliveira <[email protected]> * Update all spacing to exactly match riscv-opcodes. Signed-off-by: Afonso Oliveira <[email protected]> * Change check_requirement due to being out of scope for go_generator call. Signed-off-by: Afonso Oliveira <[email protected]> * Add gen:go to CI regression. Signed-off-by: Afonso Oliveira <[email protected]> * Add gen:go to local regression test. Signed-off-by: Afonso Oliveira <[email protected]> --------- Signed-off-by: Afonso Oliveira <[email protected]> Co-authored-by: Your Name <[email protected]>
…cv-software-src#523) fixes riscv-software-src#520 Co-authored-by: Derek Hower <[email protected]>
have you run |
Yes, I ran the |
Moved base branch to vector branch. As discussed, we will do all development for vector extension in the vector branch before we merge to main. Additionally, I wanted to ask on v.idl. Here you created v.idl, while in mine (#467) I called it vec.idl. It really doesn't matter, but we should probably stay consistent. @dhower-qc your call, what do we want to call the file? |
Does the failure occur without your changes? Does the failure occur for you on the main branch? The cpp_hart and Ruby processing is not familiar to me. In the absence of more knowledgeable guidance, it might help to bisect the branch. Are you familiar with |
I tried running it without my changes, and the failure still occurs. I used git bisect as you suggested, but I could not find any fully good commit — the error is present throughout. |
I see the same error with current "main". @dhower-qc ? |
This is reported separately as #678 |
Fixed in main. |
Hi @dhower-qc , @ThinkOpenly,
Although you previously addressed and resolved an error related to this command, I regret to inform you that I am still unable to execute it successfully, as a new error has arisen. I would appreciate the opportunity to schedule a brief meeting with you to discuss this persistent issue and to seek guidance on properly setting up the C++ Instruction Set Simulator (ISS). |
Do you mean "CONFIG=rv32"?
I was able to successfully run this just now on the branch "main" (HEAD commit cf88b2b):
The ISS is not really my area of expertise. Can you provide more details about the error you see? |
Thank you for your response! I think both commands are different:
This generation command (gen:cpp_hart) runs successfully on my laptop, so I think the setup is working fine on my side. But I get an error when using |
Objective: This pull request resolves all syntax errors detected using the
./do test:smoke
command.Instruction Implementation: Implemented RISC-V vector Arithmatic instructions
Next Action: Proceeding to validate the correctness of the implementation through simulation using the command
./do build:cpp_hart
.Current Issue: Encountering an error during the execution of
./do build:cpp_hart
, indicating that the C++ ISS (Instruction Set Simulator) is not properly work.Environment Status: Spike, QEMU, and the RISC-V GCC toolchain are already installed and available in the local environment.
Simulation Goal: The goal is to simulate the program and identify any remaining logical errors to ensure correctness.
Assistance Request: Requesting help with (i) setting up the C++ ISS, and (ii) guidance on how to define RISC-V vector registers in UDB using IDL (ISA Definition Language).