Add Smcsrind and Sscsrind CSR YAML Files

arch/csr/Smcsrind/mireg.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg
+long_name: Machine Indirect Register Alias
+address: 0x351
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description:
+  - id: csr-mireg-purpose
+    normative: true
+    text: |
+      The mireg machine indirect alias CSR is used to access another CSR's state
+      indirectly upon a read or write, as determined by the value of miselect.
+  - id: csr-mireg-unimplemented-miselect
+    normative: true
+    text: |
+      The behavior upon accessing mireg from M-mode, while miselect holds a value
+      that is not implemented, is UNSPECIFIED.
+  - id: csr-mireg-unimplemented-miselect-note
+    normative: false
+    text: |
+      It is expected that implementations will typically raise an illegal instruction exception for
+      such accesses, so that, for example, they can be identified as software bugs. Platform
+      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+      behavior for such accesses.
+  - id: csr-mireg-implemented-miselect
+    normative: true
+    text: |
+      Attempts to access mireg while miselect holds a number in an allocated and implemented range
+      results in a specific behavior that, for each combination of miselect and mireg, is defined by the
+      extension to which the miselect value is allocated.
+  - id: csr-mireg-implemented-miselect-note
+    normative: false
+    text: |
+      Ordinarily, mireg will access register state, access read-only 0 state, or raise an
+      illegal instruction exception.
+  - id: csr-mireg-rv32-64bit-access
+    normative: false
+    text: |
+      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+      recommended that the lower 32 bits of the register are accessed through mireg,
+      while the upper 32 bits are accessed through mireg4.
+fields:
+  VALUE:
+    long_name: Indirectly Selected Register Value
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description:
+      - id: csr-mireg-value-purpose
+        normative: true
+        text: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
+      if (!handle.valid) {
+        unimplemented_csr($encoding);
+      }
+      if (!handle.writable) {
+        raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+      }
+      csr_sw_write(handle, csr_value.VALUE);
+      return csr_hw_read(handle);
+sw_read(): |
+  Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
+  if (!handle.valid) {
+    unimplemented_csr($encoding);
+  }
+  return csr_sw_read(handle);

arch/csr/Smcsrind/mireg2.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg2
+long_name: Machine Indirect Register Alias 2
+address: 0x352
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description:
+  - id: csr-mireg2-purpose
+    normative: true
+    text: |
+      The `mireg2` machine indirect alias CSR is used to access register state indirectly
+      upon a read or write, as determined by the value of `miselect`.
+
+  - id: csr-mireg2-unimplemented-miselect
+    normative: true
+    text: |
+      The behavior upon accessing `mireg2` from M-mode, while `miselect` holds a value
+      that is not implemented, is UNSPECIFIED.
+
+  - id: csr-mireg2-unimplemented-miselect-typical
+    normative: false
+    text: |
+      It is expected that implementations will typically raise an illegal instruction exception for
+      such accesses, so that, for example, they can be identified as software bugs. Platform
+      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+      behavior for such accesses.
+
+  - id: csr-mireg2-implemented-miselect
+    normative: true
+    text: |
+      Attempts to access `mireg2` while `miselect` holds a number in an allocated and implemented
+      range results in a specific behavior that, for each combination of `miselect` and `mireg2`, is
+      defined by the extension to which the `miselect` value is allocated.
+
+  - id: csr-mireg2-behavior-typical
+    normative: false
+    text: |
+      Ordinarily, `mireg2` will access register state, access read-only 0 state, or raise an
+      illegal instruction exception.
+
+  - id: csr-mireg2-rv32-64bit-access
+    normative: false
+    text: |
+      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+      recommended that the lower 32 bits of the register are accessed through `mireg2`,
+      while the upper 32 bits are accessed through `mireg5`.
+
+fields:
+  VALUE:
+    long_name: Indirect Register Value
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description:
+      - id: csr-mireg2-value-purpose
+        normative: true
+        text: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
+      if (!handle.valid) {
+        unimplemented_csr($encoding);
+      }
+      if (!handle.writable) {
+        raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+      }
+      csr_sw_write(handle, csr_value.VALUE);
+      return csr_hw_read(handle);
+sw_read(): |
+  Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
+  if (!handle.valid) {
+    unimplemented_csr($encoding);
+  }
+  return csr_sw_read(handle);

arch/csr/Smcsrind/mireg3.yaml

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+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg3
+long_name: Machine Indirect Register Alias 3
+address: 0x353
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description:
+  - id: csr-mireg3-purpose
+    normative: true
+    text: |
+      The `mireg3` machine indirect alias CSR is used to access register state indirectly
+      upon a read or write, as determined by the value of `miselect`.
+
+  - id: csr-mireg3-unimplemented-miselect
+    normative: true
+    text: |
+      The behavior upon accessing `mireg3` from M-mode, while `miselect` holds a value
+      that is not implemented, is UNSPECIFIED.
+
+  - id: csr-mireg3-unimplemented-miselect-note
+    normative: false
+    text: |
+      It is expected that implementations will typically raise an illegal instruction exception for
+      such accesses, so that, for example, they can be identified as software bugs. Platform
+      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+      behavior for such accesses.
+
+  - id: csr-mireg3-implemented-miselect
+    normative: true
+    text: |
+      Attempts to access `mireg3` while `miselect` holds a number in an allocated and implemented
+      range results in a specific behavior that, for each combination of `miselect` and `mireg3`, is
+      defined by the extension to which the `miselect` value is allocated.
+
+  - id: csr-mireg3-implemented-miselect-note
+    normative: false
+    text: |
+      Ordinarily, `mireg3` will access register state, access read-only 0 state, or raise an
+      illegal instruction exception.
+
+  - id: csr-mireg3-rv32-64bit-access
+    normative: false
+    text: |
+      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+      recommended that the lower 32 bits of the register are accessed through `mireg3`,
+      while the upper 32 bits are accessed through `mireg6`.
+
+fields:
+  VALUE:
+    long_name: Indirectly Selected Register Value
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description:
+      - id: csr-mireg3-value-purpose
+        normative: true
+        text: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
+      if (!handle.valid) {
+        unimplemented_csr($encoding);
+      }
+      if (!handle.writable) {
+        raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+      }
+      csr_sw_write(handle, csr_value.VALUE);
+      return csr_hw_read(handle);
+sw_read(): |
+  Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
+  if (!handle.valid) {
+    unimplemented_csr($encoding);
+  }
+  return csr_sw_read(handle);

arch/csr/Smcsrind/mireg4.yaml

@@ -0,0 +1,77 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg4
+long_name: Machine Indirect Register Alias 4
+address: 0x355
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description:
+  - id: csr-mireg4-purpose
+    normative: true
+    text: |
+      The `mireg4` machine indirect alias CSR is used to access register state indirectly
+      upon a read or write, as determined by the value of `miselect`.
+
+  - id: csr-mireg4-unimplemented-miselect
+    normative: true
+    text: |
+      The behavior upon accessing `mireg4` from M-mode, while `miselect` holds a value
+      that is not implemented, is UNSPECIFIED.
+
+  - id: csr-mireg4-unimplemented-miselect-note
+    normative: false
+    text: |
+      It is expected that implementations will typically raise an illegal instruction exception for
+      such accesses, so that, for example, they can be identified as software bugs. Platform
+      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+      behavior for such accesses.
+
+  - id: csr-mireg4-implemented-miselect
+    normative: true
+    text: |
+      Attempts to access `mireg4` while `miselect` holds a number in an allocated and implemented
+      range results in a specific behavior that, for each combination of `miselect` and `mireg4`, is
+      defined by the extension to which the `miselect` value is allocated.
+
+  - id: csr-mireg4-implemented-miselect-note
+    normative: false
+    text: |
+      Ordinarily, `mireg4` will access register state, access read-only 0 state, or raise an
+      illegal instruction exception.
+
+  - id: csr-mireg4-rv32-64bit-access
+    normative: false
+    text: |
+      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+      recommended that the upper 32 bits of the register are accessed through `mireg4`,
+      while the lower 32 bits are accessed through `mireg`, `mireg2`, or `mireg3`.
+
+fields:
+  VALUE:
+    long_name: Indirectly Selected Register Value
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description:
+      - id: csr-mireg4-value-purpose
+        normative: true
+        text: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
+      if (!handle.valid) {
+        unimplemented_csr($encoding);
+      }
+      if (!handle.writable) {
+        raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+      }
+      csr_sw_write(handle, csr_value.VALUE);
+      return csr_hw_read(handle);
+sw_read(): |
+  Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
+  if (!handle.valid) {
+    unimplemented_csr($encoding);
+  }
+  return csr_sw_read(handle);

arch/csr/Smcsrind/mireg5.yaml

@@ -0,0 +1,77 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mireg5
+long_name: Machine Indirect Register Alias 5
+address: 0x356
+priv_mode: M
+length: MXLEN
+definedBy: Smcsrind
+description:
+  - id: csr-mireg5-purpose
+    normative: true
+    text: |
+      The `mireg5` machine indirect alias CSR is used to access register state indirectly
+      upon a read or write, as determined by the value of `miselect`.
+
+  - id: csr-mireg5-unimplemented-miselect
+    normative: true
+    text: |
+      The behavior upon accessing `mireg5` from M-mode, while `miselect` holds a value
+      that is not implemented, is UNSPECIFIED.
+
+  - id: csr-mireg5-unimplemented-miselect-note
+    normative: false
+    text: |
+      It is expected that implementations will typically raise an illegal instruction exception for
+      such accesses, so that, for example, they can be identified as software bugs. Platform
+      specs, profile specs, and/or the Privileged ISA spec may place more restrictions on
+      behavior for such accesses.
+
+  - id: csr-mireg5-implemented-miselect
+    normative: true
+    text: |
+      Attempts to access `mireg5` while `miselect` holds a number in an allocated and implemented
+      range results in a specific behavior that, for each combination of `miselect` and `mireg5`, is
+      defined by the extension to which the `miselect` value is allocated.
+
+  - id: csr-mireg5-implemented-miselect-note
+    normative: false
+    text: |
+      Ordinarily, `mireg5` will access register state, access read-only 0 state, or raise an
+      illegal instruction exception.
+
+  - id: csr-mireg5-rv32-64bit-access
+    normative: false
+    text: |
+      For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is
+      recommended that the upper 32 bits of the register are accessed through `mireg5`,
+      while the lower 32 bits are accessed through `mireg2`.
+
+fields:
+  VALUE:
+    long_name: Indirectly Selected Register Value
+    location_rv32: 31-0
+    location_rv64: 63-0
+    type: RW
+    description:
+      - id: csr-mireg5-value-purpose
+        normative: true
+        text: Register state of the CSR selected by the current `miselect` value
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
+      if (!handle.valid) {
+        unimplemented_csr($encoding);
+      }
+      if (!handle.writable) {
+        raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
+      }
+      csr_sw_write(handle, csr_value.VALUE);
+      return csr_hw_read(handle);
+sw_read(): |
+  Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
+  if (!handle.valid) {
+    unimplemented_csr($encoding);
+  }
+  return csr_sw_read(handle);