Merge pull request #442 from riscv-software-src/Xqciv0p6

Xqci extension: version 0.6 fixes: fixing qc.c.mveqz and qc.c.muliadd…
riscv-software-src · Jan 29, 2025 · a4dbe34 · a4dbe34
2 parents bfda3e5 + dfec062
commit a4dbe34
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Showing 12 changed files with 68 additions and 104 deletions.
diff --git a/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml b/cfgs/qc_iu/arch_overlay/csr/Xqci/qc_flags.yaml
diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqci.yaml
@@ -149,8 +149,13 @@ versions:
   changes:
     - Fix encoding of qc.c.extu instruction
     - Fix encoding of qc.swmi instruction
+    - Fix decoding of qc.pputci instruction
+    - Fix decoding of qc.delay instruction (state that immediate cannot be 0)
     - Rename qc.slasat -> qc.shlsat
     - Rename qc.sllsat -> qc.shlusat
+    - Add requirement to include Zca extension for Xqcisim since it has 16-bit instructions
+    - Add requirement to include Zca extension for Xqcisync since it has 16-bit instructions
+    - Remove qc.flags CSR
   implies:
   - [Xqcia, "0.4.0"]
   - [Xqciac, "0.2.0"]
@@ -159,14 +164,16 @@ versions:
   - [Xqcicli, "0.2.0"]
   - [Xqcicm, "0.2.0"]
   - [Xqcics, "0.2.0"]
-  - [Xqcicsr, "0.2.0"]
+  - [Xqcicsr, "0.3.0"]
   - [Xqciint, "0.2.0"]
   - [Xqcilb, "0.2.0"]
   - [Xqcili, "0.2.0"]
   - [Xqcilia, "0.2.0"]
   - [Xqcilo, "0.2.0"]
   - [Xqcilsm, "0.4.0"]
+  - [Xqcisim, "0.2.0"]
   - [Xqcisls, "0.2.0"]
+  - [Xqcisync, "0.2.0"]
   requires:
     name: Zca
     version: ">= 1.0.0"

diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcicsr.yaml
@@ -28,6 +28,18 @@ versions:
     email: [email protected]
   changes:
     - Add information about instruction formats of each instruction
+- version: "0.3.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Remove qc.flags CSR
 description: |
   The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate.
 

diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisim.yaml
@@ -16,6 +16,20 @@ versions:
   - name: Derek Hower
     company: Qualcomm Technologies, Inc.
     email: [email protected]
+- version: "0.2.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix decoding of qc.pputci instruction
+    - Add requirement to include Zca extension since has 16-bit instructions
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcisim extension includes ten hint instructions to interface simulation environment.
   On real target any instruction from this extension executed as "no-operation" and have no effect.

diff --git a/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml b/cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml
@@ -16,6 +16,20 @@ versions:
   - name: Derek Hower
     company: Qualcomm Technologies, Inc.
     email: [email protected]
+- version: "0.2.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix decoding of qc.delay instruction (state that immediate cannot be 0)
+    - Add requirement to include Zca extension since has 16-bit instructions
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction.
   Synchronization instructions are kind of IO fences that work with special devices synchronization signals.

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml
@@ -18,6 +18,7 @@ encoding:
   variables:
     - name: imm
       location: 6-2
+      not: 0
 access:
   s: always
   u: always

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.nest.yaml
@@ -25,7 +25,7 @@ operation(): |
   XReg mepc_val = CSR[mepc].sw_read();
   XReg mnepc_val = CSR[qc_mnepc].sw_read();
   XReg mcause_val = CSR[mcause].sw_read();
-  XReg flags_val = CSR[qc_flags].sw_read();
+  XReg reserved_val = 0;
   if (CSR[mcause].NMI != 1'b1) {
     write_memory<32>(virtual_address -  4, mepc_val, $encoding);
   } else {
@@ -34,7 +34,7 @@ operation(): |
   write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
   write_memory<32>(virtual_address - 12, mcause_val, $encoding);
   write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, flags_val, $encoding);
+  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
   write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
   write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
   write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mienter.yaml
@@ -27,7 +27,7 @@ operation(): |
   XReg mepc_val = CSR[mepc].sw_read();
   XReg mnepc_val = CSR[qc_mnepc].sw_read();
   XReg mcause_val = CSR[mcause].sw_read();
-  XReg flags_val = CSR[qc_flags].sw_read();
+  XReg reserved_val = 0;
   if (CSR[mcause].NMI != 1'b1) {
     write_memory<32>(virtual_address -  4, mepc_val, $encoding);
   } else {
@@ -36,7 +36,7 @@ operation(): |
   write_memory<32>(virtual_address -  8, X[ 8][31:0], $encoding);
   write_memory<32>(virtual_address - 12, mcause_val, $encoding);
   write_memory<32>(virtual_address - 16, X[ 1][31:0], $encoding);
-  write_memory<32>(virtual_address - 20, flags_val, $encoding);
+  write_memory<32>(virtual_address - 20, reserved_val, $encoding);
   write_memory<32>(virtual_address - 24, X[ 5][31:0], $encoding);
   write_memory<32>(virtual_address - 28, X[ 6][31:0], $encoding);
   write_memory<32>(virtual_address - 32, X[ 7][31:0], $encoding);

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mileaveret.yaml
@@ -33,7 +33,6 @@ operation(): |
   X[ 8] = read_memory<32>(virtual_address -  8, $encoding);
   CSR[mcause].sw_write(read_memory<32>(virtual_address - 12, $encoding));
   X[ 1] = read_memory<32>(virtual_address - 16, $encoding);
-  CSR[qc_flags].sw_write(read_memory<32>(virtual_address - 20, $encoding));
   X[ 5] = read_memory<32>(virtual_address - 24, $encoding);
   X[ 6] = read_memory<32>(virtual_address - 28, $encoding);
   X[ 7] = read_memory<32>(virtual_address - 32, $encoding);

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml
@@ -8,14 +8,13 @@ description: |
   Increments `rd` by the multiplication of `rs1` and an unsigned immediate
   Instruction encoded in CL instruction format.
 definedBy:
-  allOf:
-    - not:
-        anyOf:
-          - allOf: [C, D]
-          - Zcd
-    - anyOf:
-        - Xqci
-        - Xqciac
+  anyOf:
+    - Xqci
+    - Xqciac
+excludedBy:
+  anyOf:
+    - allOf: [C, D]
+    - Zcd
 base: 32
 encoding:
   match: 001-----------10

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml
@@ -8,14 +8,13 @@ description: |
   Move `rs1` to `rd` if `rd` == 0, keep `rd` value otherwise
   Instruction encoded in CL instruction format.
 definedBy:
-  allOf:
-    - anyOf:
-        - Xqci
-        - Xqcicm
-    - not:
-        anyOf:
-          - allOf: [C, D]
-          - Zcd
+  anyOf:
+    - Xqci
+    - Xqciac
+excludedBy:
+  anyOf:
+    - allOf: [C, D]
+    - Zcd
 base: 32
 encoding:
   match: 101011---00---10

diff --git a/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml b/cfgs/qc_iu/arch_overlay/inst/Xqci/qc.pputci.yaml
@@ -18,7 +18,7 @@ encoding:
   match: 0100--------00000010000000010011
   variables:
     - name: imm
-      location: 29-20
+      location: 27-20
 access:
   s: always
   u: always