Merge remote-tracking branch 'origin/master' into kathlenem/vlsu

riscv-software-src · Nov 7, 2024 · 52bcafa · 52bcafa
2 parents ebd74dd + 8f9e442
commit 52bcafa
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diff --git a/arches/big_core.yaml b/arches/big_core.yaml
@@ -40,18 +40,34 @@ top.cpu.core0.extension.core_extensions:
   # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
   # if you want just one execution unit to issue queue you can do:
   # ["0"] which would result in iq0 -> exe0
-  # *note if you change the number of issue queues, 
+  # *note if you change the number of issue queues,
   # you need to add it to latency matrix below
 
   issue_queue_to_pipe_map:
-  [ 
+  [
     ["0", "1"], # iq0 -> exe0, exe1
     ["2", "3"], # iq1 -> exe2, exe3
     ["4", "5"], # iq2 -> exe4, exe5
     ["6", "7"], # iq3 -> exe6, exe7
     ["8", "9"],  # iq4 -> exe8, exe9
     ["10"] # iq5 -> exe10
   ]
+
+  exe_pipe_rename:
+    [
+      ["exe0", "sys_pipe"],
+      ["exe1", "alu1_pipe"],
+      ["exe2", "alu2_pipe"],
+      ["exe3", "alu3_pipe"],
+      ["exe4", "alu4_pipe"],
+      ["exe5", "alu5_pipe"],
+      ["exe6", "fpu0_pipe"],
+      ["exe7", "fpu1_pipe"],
+      ["exe8", "br0_pipe"],
+      ["exe9", "br1_pipe"],
+      ["exe10", "vint_pipe"]
+    ]
+
 top.cpu.core0.rename.scoreboards:
   # From
   # |

diff --git a/arches/isa_json/gen_uarch_rv64v_json.py b/arches/isa_json/gen_uarch_rv64v_json.py
@@ -209,7 +209,21 @@
     "vmv.v.x" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1},
     "vmv.v.i" : {"pipe" : "vint", "uop_gen" : "ARITH", "latency" : 1},
 
-# TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Saturating Add and Subtract
+# Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Saturating Add and Subtract
+    "vsaddu.vv" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vsaddu.vx" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vsaddu.vi" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+
+    "vsadd.vv" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vsadd.vx" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vsadd.vi" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+
+    "vssubu.vv" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vssubu.vx" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+
+    "vssub.vv" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+    "vssub.vx" : {"pipe" : "vfixed", "uop_gen" : "ARITH", "latency" : 1},
+
 # TODO: Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Averaging Add and Subtract
 # Vector Fixed-Point Arithmetic Instructions: Vector Single-Width Fractional Multiply with Rounding and Saturation
     "vsmul.vx" :   {"pipe" : "vmul", "uop_gen" : "ARITH", "latency" : 3},

diff --git a/arches/isa_json/olympia_uarch_rv64v.json b/arches/isa_json/olympia_uarch_rv64v.json
@@ -1645,39 +1645,39 @@
     },
     {
         "mnemonic": "vsadd.vi",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsadd.vv",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsadd.vx",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsaddu.vi",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsaddu.vv",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsaddu.vx",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsbc.vvm",
@@ -1945,27 +1945,27 @@
     },
     {
         "mnemonic": "vssub.vv",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vssub.vx",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vssubu.vv",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vssubu.vx",
-        "pipe": "?",
-        "uop_gen": "NONE",
-        "latency": 0
+        "pipe": "vint",
+        "uop_gen": "ARITH",
+        "latency": 1
     },
     {
         "mnemonic": "vsub.vv",

diff --git a/arches/medium_core.yaml b/arches/medium_core.yaml
@@ -29,22 +29,33 @@ top.cpu.core0.extension.core_extensions:
       ["br"], # exe5
       ["vint", "vset", "vdiv", "vmul"] # exe6
   ]
-  
+
   # this is used to set how many units per queue
   # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
   # if you want just one execution unit to issue queue you can do:
   # ["0"] which would result in iq0 -> exe0
-  # *note if you change the number of issue queues, 
+  # *note if you change the number of issue queues,
   # you need to add it to latency matrix below
   issue_queue_to_pipe_map:
-  [ 
+  [
     ["0"], # iq0 -> exe0
     ["1", "2"], # iq1 -> exe1, exe2
     ["3", "4"], # iq2 -> exe3, exe4
     ["5"], # iq3 -> exe5
     ["6"]
   ]
 
+  exe_pipe_rename:
+    [
+      ["exe0", "alu0_pipe"],
+      ["exe1", "alu1_pipe"],
+      ["exe2", "alu2_pipe"],
+      ["exe3", "fpu0_pipe"],
+      ["exe4", "fpu1_pipe"],
+      ["exe5", "br_pipe"],
+      ["exe6", "vint_pipe"]
+    ]
+
 top.cpu.core0.rename.scoreboards:
   # From
   # |

diff --git a/arches/small_core.yaml b/arches/small_core.yaml
@@ -27,16 +27,25 @@ top.cpu.core0.extension.core_extensions:
   # ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
   # if you want just one execution unit to issue queue you can do:
   # ["0"] which would result in iq0 -> exe0
-  # *note if you change the number of issue queues, 
+  # *note if you change the number of issue queues,
   # you need to add it to latency matrix below
   issue_queue_to_pipe_map:
-  [ 
+  [
     ["0"], # iq0 -> exe0
     ["1"], # iq1 -> exe1
     ["2"], # iq2 -> exe2
     ["3"], # iq3 -> exe3
   ]
 
+  exe_pipe_rename:
+    [
+      ["exe0", "alu0_pipe"],
+      ["exe1", "fpu0_pipe"],
+      ["exe2", "br_pipe"],
+      ["exe3", "vint_pipe"]
+    ]
+
+
 top.cpu.core0.rename.scoreboards:
   # From
   # |

diff --git a/conda/README.md b/conda/README.md
@@ -13,9 +13,9 @@ If `conda` is not already set up or the preference is to have a local
 
 ## Create a New Environment or Update Existing Conda Environment
 
-** If these steps do no work, follow the directions on
-   [Map/Sparta](https://github.com/sparcians/map/tree/master#building-map)
-   instead **
+**If these steps do no work, follow the directions on
+  [Map/Sparta](https://github.com/sparcians/map/tree/master#building-map)
+  instead**
 
 A new environment can be created using `environment.yaml` file as follows:
 
@@ -31,4 +31,8 @@ If an environment named `riscv_perf_model` exists, it can be updated as follows:
 conda env update --file environment.yml  --prune
 ```
 
-Thw file `environment_from_history.yml` provides a minimal specification, in case, there is a need to build the conda environment from scratch.
+The file `environment_for_macos.yml` provides an alternative specification if encountering problems
+while building the conda environement for macOS.
+
+The file `environment_from_history.yml` provides a minimal specification, in case, there is a need
+to build the conda environment from scratch.