add decode logic for cbo.* instructions in the decoder plugin

CHANGELOG.md

@@ -2,6 +2,8 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.16.2] - 2022-12-09
+- Add decode logic for cbo.* instructions in the decoder plugin
 
 ## [0.16.1] - 2022-10-20
 - Fix length of commitval to 32 bits if flen is 32 for f registers in sail parser.
@@ -19,6 +21,7 @@ This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.htm
 - Add fields(frm, fcsr, nan_prefix) for fp instructions
 
 ## [0.13.2] - 2022-05-23
+
 - Error reporting for missing coverlabel in cgf file
 
 ## [0.13.1] - 2022-05-07

riscv_isac/InstructionObject.py

@@ -165,6 +165,9 @@ def evaluate_instr_vars(self, xlen, flen, arch_state, csr_regfile, instr_vars):
         if self.instr_name in ['ld','sd','fld','fsd']:
             ea_align = (rs1_val + imm_val) % 8
 
+        if self.instr_name == "cbo.zero":
+            rs1_val = rs1_val & 0xFFF
+
         instr_vars.update({
             'rs1_val': rs1_val,
             'rs2_val': rs2_val,

riscv_isac/__init__.py

@@ -4,5 +4,5 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = '[email protected]'
-__version__ = '0.16.1'
+__version__ = '0.16.2'
 

riscv_isac/plugins/internaldecoder.py

@@ -13,7 +13,7 @@ def __init__(self):
             0b0100011: self.store_ops,
             0b0010011: self.arithi_ops,
             0b0110011: self.arith_ops,
-            0b0001111: self.fence_ops,
+            0b0001111: self.fence_cbo_ops,
             0b1110011: self.priviledged_ops,
             0b0011011: self.rv64i_arithi_ops,
             0b0111011: self.rv64i_arith_ops,
@@ -1310,19 +1310,34 @@ def arith_ops(self, instrObj):
 
         return instrObj
 
-    def fence_ops(self, instrObj):
+    def fence_cbo_ops(self, instrObj):
         instr = instrObj.instr
         funct3 = (instr & self.FUNCT3_MASK) >> 12
+        rd = (instr & self.RD_MASK) >> 7
+        cbo_op = instr >> 20
 
         pred = (instr >> 20) & 0x0000000f
         succ = (instr >> 24) & 0x0000000f
 
+        rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
+
         if funct3 == 0b000:
             instrObj.succ = succ
             instrObj.pred = pred
             instrObj.instr_name = 'fence'
         if funct3 == 0b001:
             instrObj.instr_name = 'fence.i'
+        if funct3 == 0b010:
+            if rd == 0:
+                instrObj.rs1 = rs1
+                if cbo_op == 0b000000000001:
+                    instrObj.instr_name = 'cbo.clean'
+                if cbo_op == 0b000000000010:
+                    instrObj.instr_name = 'cbo.flush'
+                if cbo_op == 0b000000000000:
+                    instrObj.instr_name = 'cbo.inval'
+                if cbo_op == 0b000000000100:
+                    instrObj.instr_name = 'cbo.zero'
 
         return instrObj
 

setup.cfg

@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.16.1
+current_version = 0.16.2
 commit = True
 tag = True
 

setup.py

@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_isac',
-    version='0.16.1',
+    version='0.16.2',
     description="RISC-V ISAC",
     long_description=readme + '\n\n',
     classifiers=[