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updates for crypto scalar instructions #34

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updates for crypto scalar instructions #34

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2b3748a
1) pack and zext.h have same opcode, func3, funct7 only diffrence is…
anku-anand Mar 28, 2022
1b14576
Merge branch 'master' of https://github.com/anku-anand/riscv-isac
anku-anand Mar 28, 2022
aa98e42
using isa to differentiate between zext.h and pack, packw instructions
anku-anand Apr 11, 2022
9ff4563
Merge branch 'riscv-software-src:master' into master
anku-anand May 22, 2022
c82d51f
Added gorci to unsgn_rs1 in coverage.py
anku-anand May 24, 2022
a0b076c
removed isa argument from decoder plugin setup
anku-anand May 29, 2022
16ddd43
Merge branch 'master' into master
anku-anand Sep 8, 2022
5aaf74c
update CHANGELOG.md
anku-anand Sep 8, 2022
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7 changes: 4 additions & 3 deletions riscv_isac/coverage.py
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Original file line number Diff line number Diff line change
Expand Up @@ -36,14 +36,15 @@
'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
'bset','zext.h','sext.h','sext.b','minu','maxu','orc.b','add.uw','sh1add.uw',\
'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
'bclri','bexti','binvi','bseti']
'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip']
unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\
'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\
'aes64esm','aes64ks2','sm4ed','sm4ks','ror','rol','rorw','rolw','clmul',\
'clmulh','clmulr','andn','orn','xnor','pack','packh','packu','packuw','packw',\
'xperm.n','xperm.b', 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi',\
'sha512sum1r','sha512sum0r','sha512sig1l','sha512sig1h','sha512sig0l','sha512sig0h','fsw',\
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw']
'bclr','bext','binv','bset','minu','maxu','add.uw','sh1add.uw','sh2add.uw','sh3add.uw',\
'xperm4','xperm8','zip','unzip']

class cross():

Expand Down Expand Up @@ -940,7 +941,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle
decoderclass = getattr(instructionObjectfile, "disassembler")
decoder_pm.register(decoderclass())
decoder = decoder_pm.hook
decoder.setup(arch="rv"+str(xlen))
decoder.setup(arch="rv"+str(xlen),labels=cov_labels)

iterator = iter(parser.__iter__()[0])
rcgf = cgf
Expand Down
23 changes: 15 additions & 8 deletions riscv_isac/plugins/internaldecoder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -406,8 +406,9 @@ def init_rvp_dictionary(self):
self.rvp_dict_11[0x00003077] = 'bpick'

@plugins.decoderHookImpl
def setup(self, arch):
def setup(self, arch,labels):
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self.arch = arch
self.labels = labels

FIRST2_MASK = 0x00000003
OPCODE_MASK = 0x0000007f
Expand Down Expand Up @@ -598,10 +599,10 @@ def arithi_ops(self, instrObj):

if funct3 == 0b001:
if funct7 == 0b0000100:
if instrObj.arch == 'rv32':
instrObj.instr_name = 'zip'
instrObj.rs1= rs1
instrObj.rd = rd
if self.arch == 'rv32':
instrObj.instr_name = 'zip'
instrObj.rs1= rs1
instrObj.rd = rd
elif sbi == 0b0100100 or sbi == 0b010010:
instrObj.rs1 = rs1
instrObj.rd = rd
Expand Down Expand Up @@ -720,7 +721,7 @@ def arithi_ops(self, instrObj):

if funct3 == 0b101:
if funct7 == 0b0000100:
if instrObj.arch == 'rv32':
if self.arch == 'rv32':
instrObj.instr_name = 'unzip'
instrObj.rs1= rs1
instrObj.rd = rd
Expand Down Expand Up @@ -1210,7 +1211,10 @@ def arith_ops(self, instrObj):
instrObj.rs2 = rs2
instrObj.rd = rd
elif funct7 == 0b0000100:
if rs2[0] == 0b0:
# pack and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
# for zext.h rs2 is always 0, if pack instruction is used with x0 as rs2
# then cannot distinguish from each other, hence using cover label to differentiate.
if rs2[0] == 0b0 and "pack" not in self.labels:
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instrObj.instr_name = 'zext.h'
instrObj.rs1 = rs1
instrObj.rd = rd
Expand Down Expand Up @@ -1499,7 +1503,10 @@ def rv64i_arith_ops(self, instrObj):

if funct3 == 0b100:
if funct7 == 0b0000100:
if rs2[0] == 0b0:
# packw and zext.h have same opcode, func3, funct7 only diffrence is in rs2 value
# for zext.h rs2 is always 0, if packw instruction is used with x0 as rs2
# then cannot distinguish from each other, hence using cover label to differentiate.
if rs2[0] == 0b0 and "packw" not in self.labels:
instrObj.instr_name = 'zext.h'
instrObj.rs1 = rs1
instrObj.rd = rd
Expand Down
4 changes: 2 additions & 2 deletions riscv_isac/plugins/specification.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

class DecoderSpec(object):
@decoderHookSpec
def setup(self,arch):
def setup(self,arch,labels):
pass

@decoderHookSpec
Expand All @@ -19,4 +19,4 @@ def setup(self,trace,arch):

@parserHookSpec
def __iter__(self):
pass
pass