Semihosting for RISC-V processors
This is a fork of the cortex-m-semihosting crate with changes to support the RISC-V Semihosting Specification as documented here
This crate can (almost) be used in exactly the same way as cortex-m-semihosting,
simply by changing calls to cortex_m_semihosting::* to riscv_semihosting::*.
Given this, the
cortex-m-semihosting documentation is
generally sufficient for using this library.
A major difference between this library and cortex-m-semihosting is that there
are mandatory features to choose the privilege level at which the semihosting
calls are executed. The "machine-mode" feature will cause the macros in export
to execute the semihosting operation in an interrupt-free context, while
"user-mode" causes them to just execute the operation. Failure to select one of
these two features will cause a compiler error.
This crate is guaranteed to compile on stable Rust 1.59.0 and up. It won't compile with older versions.
Licensed under either of
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.
Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.