expand imp_id to 32 bits

riscv-non-isa · Mar 21, 2024 · 7db3f25 · 7db3f25
1 parent b93ef79
commit 7db3f25
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/reri_err_reporting.adoc b/reri_err_reporting.adoc
@@ -144,9 +144,8 @@ The `vendor_n_imp_id` register is a read-only register and its layout is:
 ....
 {reg: [
   {bits: 32, name: 'vendor_id'},
-  {bits: 16, name: 'imp_id'},
-  {bits: 16, name: 'WPRI'},
-], config:{lanes: 2, hspace:1024}}
+  {bits: 32, name: 'imp_id'},
+], config:{lanes: 1, hspace:1024}}
 ....
 
 The `vendor_id` field follows the encoding as defined by `mvendorid` CSR and