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59 Open 207 Closed
59 Open 207 Closed
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Issues list

Need help on coverage mode test
#542 opened Oct 23, 2024 by trdthg
5
Some test cases of 32h cannot generate data normally
#531 opened Oct 18, 2024 by Pagerd
Add CI for format/lint
#525 opened Oct 16, 2024 by trdthg
3
Error: illegal operands when trying to running floating-point testscase when using TEST_FPSR_OP
#498 opened Sep 29, 2024 by Pagerd
2
Unable to locate Vector Extension Test Suites
#491 opened Sep 9, 2024 by SyedHassanUlHaq
1
Missing coverage for compressed illegal instruction
#482 opened Jul 25, 2024 by Bill94l
Dup RVMODEL_BOOT macros crashes compile on DUT.
#479 opened Jul 15, 2024 by InspireSemi
1
ACT should remove explicit RVMODEL_HALT and instead add it to the end of RVTEST_CODE_END
#477 opened Jul 1, 2024 by allenjbaum
ACT should pick different Canary to be the identifier for the end of each test case
#475 opened Jun 17, 2024 by jamesbeyond
Cover Group files are scattered in different directories
#460 opened Apr 24, 2024 by allenjbaum
2
Error in CTG commands for generating floating point riscv-tests
#459 opened Apr 24, 2024 by Shreesh-Kulkarni
4
Zfh tests missing floating-to-float conversions
#458 opened Apr 23, 2024 by davidharrishmc
Regnerated MUL* tests missing Zmmul string in RVTEST_ISA macro
#457 opened Apr 23, 2024 by allenjbaum
Zfa tests missing fmvp.d.x
#456 opened Apr 22, 2024 by davidharrishmc
2
Compliance command failure
#452 opened Apr 10, 2024 by T0288827
4
RVTEST_CODE_END use of RVTEST_SAVE_GPRS in env/arch_test.h doesn't work
#450 opened Apr 3, 2024 by ssecatch-w
4
Extra spaces at the end of a multiline macro causing compile warnings for env/test_macros.h
#449 opened Apr 3, 2024 by ssecatch-w
misalign-jal-01.S without support for compressed instruction signature mismatch
#445 opened Mar 17, 2024 by ArbnorSh
5
mode bits inside "vector" entry in signature
#441 opened Mar 11, 2024 by silabs-kjetil
ecall check fails in CLIC mode
#440 opened Mar 11, 2024 by silabs-kjetil
5
Atomic Test cases for amominu (and potentially others) Sail is not generating the correect signature
#430 opened Jan 23, 2024 by InspireSemi
1
Continued missing coverage for x0/non-x0 on registers (when all registers are the same)
#429 opened Jan 16, 2024 by ssecatch-w
Hypervisor Extension enable issue
#414 opened Nov 30, 2023 by Allen-StarFive
5
Need to check minsret for all tests that have deterministic# of instructioni
#408 opened Nov 13, 2023 by allenjbaum
How to generate tests for RV64D and RV64F using riscv-ctg?
#400 opened Oct 17, 2023 by riscvzbs
5
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