libgloss: Fix riscv semihost trap instructions should be all 32bit

This may not be 32bit when Zc enabled, so we need to disable zc instructions see https://github.com/riscv-non-isa/riscv-semihosting/blob/main/binary-interface.adoc https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#arch Signed-off-by: Huaqi Fang <[email protected]>
riscv-mcu · Feb 2, 2024 · 9f1e0f7 · 9f1e0f7
1 parent e901190
commit 9f1e0f7
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/libgloss/riscv/semihost_syscall.h b/libgloss/riscv/semihost_syscall.h
@@ -19,6 +19,8 @@ __semihost_syscall (long id, long *data_block)
     ".balign 16             \n"
     ".option push           \n"
     ".option norvc          \n"
+    ".option arch,-c        \n"
+    ".option arch,-zcmt,-zcmp,-zcd,-zcf,-zcb,-zca \n"
     "slli zero, zero, 0x1f  \n"
     "ebreak                 \n"
     "srai zero, zero, 0x7   \n"