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Release v3.0.1
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@renesas-fsp-development
renesas-fsp-development committed Jun 3, 2021
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4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe

### Current Release

[FSP v3.0.0](https://github.com/renesas/fsp/releases/tag/v3.0.0)
[FSP v3.0.1](https://github.com/renesas/fsp/releases/tag/v3.0.1)

### Supported RA MCU Kits

Expand Down Expand Up @@ -48,7 +48,7 @@ If you have already installed a previous FSP release that included e² studio th

#### For new users that are using FSP with e² studio

1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v3.0.0).
1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v3.0.1).
2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.

#### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####
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8 changes: 5 additions & 3 deletions ra/fsp/inc/api/r_ptp_api.h
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Expand Up @@ -114,7 +114,7 @@ typedef enum e_ptp_port_state
/** Configure the PTP instance to operate as a E2E Master. */
PTP_PORT_STATE_E2E_MASTER = (PTP_PORT_STATE_GENERATE_ANNOUNCE |
PTP_PORT_STATE_GENERATE_SYNC |
PTP_PORT_STATE_PROCESS_DELAY_RESP |
PTP_PORT_STATE_PROCESS_DELAY_REQ |
PTP_PORT_STATE_PASSIVE),

/** Configure the PTP instance to operate as a E2E Slave. */
Expand All @@ -128,15 +128,17 @@ typedef enum e_ptp_port_state
PTP_PORT_STATE_P2P_MASTER = (PTP_PORT_STATE_GENERATE_ANNOUNCE |
PTP_PORT_STATE_GENERATE_SYNC |
PTP_PORT_STATE_GENERATE_PDELAY_REQ |
PTP_PORT_STATE_PROCESS_DELAY_RESP |
PTP_PORT_STATE_PROCESS_PDELAY_REQ |
PTP_PORT_STATE_PROCESS_PDELAY_RESP |
PTP_PORT_STATE_PROCESS_PDELAY_RESP_FOLLOW_UP |
PTP_PORT_STATE_PASSIVE),

/** Configure the PTP instance to operate as a P2P Slave. */
PTP_PORT_STATE_P2P_SLAVE = (PTP_PORT_STATE_GENERATE_PDELAY_REQ |
PTP_PORT_STATE_PROCESS_SYNC |
PTP_PORT_STATE_PROCESS_FOLLOW_UP |
PTP_PORT_STATE_PROCESS_DELAY_RESP |
PTP_PORT_STATE_PROCESS_PDELAY_REQ |
PTP_PORT_STATE_PROCESS_PDELAY_RESP |
PTP_PORT_STATE_PROCESS_PDELAY_RESP_FOLLOW_UP |
PTP_PORT_STATE_PASSIVE),

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6 changes: 3 additions & 3 deletions ra/fsp/inc/fsp_version.h
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Expand Up @@ -44,16 +44,16 @@
#define FSP_VERSION_MINOR (0U)

/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
#define FSP_VERSION_PATCH (1U)

/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)

/** Public FSP version name. */
#define FSP_VERSION_STRING ("3.0.0")
#define FSP_VERSION_STRING ("3.0.1")

/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.0.0")
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.0.1")

/**********************************************************************************************************************
* Typedef definitions
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55 changes: 27 additions & 28 deletions ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
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Expand Up @@ -989,52 +989,52 @@ typedef struct
{
union
{
__IM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */
__IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */

struct
{
__IM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
uint32_t : 1;
__IM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
__IM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
__IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */
uint32_t : 1;
__IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */
__IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */
} ID_b;
};

union
{
__IM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */
__IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */

struct
{
__IM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
uint32_t : 12;
__IM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
__IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */
uint32_t : 12;
__IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */
} PTR_b;
};

union
{
__IM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */
__IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */

struct
{
__IM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
__IM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
__IM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
uint32_t : 5;
__IM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
uint32_t : 6;
__IM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
__IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */
__IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */
__IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */
uint32_t : 5;
__IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */
uint32_t : 6;
__IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */
} FDSTS_b;
};

union
{
__IM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */
__IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */

struct
{
__IM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
__IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */
} DF_b[64];
};
__IM uint32_t RESERVED[13];
Expand Down Expand Up @@ -6235,24 +6235,23 @@ typedef struct /*!< (@ 0x400B0000) R_CANFD Structure
__IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */
__IM uint32_t RESERVED41[3072];
__IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */
__IM uint32_t RESERVED42[8];
__IOM R_CANFD_CFDCF_Type CFDCF[5]; /*!< (@ 0x00006420) Common FIFO Access Registers */
__IM uint32_t RESERVED43[1624];
__IOM R_CANFD_CFDCF_Type CFDCF[5]; /*!< (@ 0x00006400) Common FIFO Access Registers */
__IM uint32_t RESERVED42[1632];
__IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */
__IM uint32_t RESERVED44[252];
__IM uint32_t RESERVED43[252];

union
{
__IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */
__IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */

struct
{
__IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
__IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */
} CFDRPGACC_b[64];
};
__IM uint32_t RESERVED45[7872];
__IOM R_CANFD_CFDTM_Type CFDTM[32]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */
} R_CANFD_Type; /*!< Size = 69632 (0x11000) */
__IM uint32_t RESERVED44[7872];
__IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */
} R_CANFD_Type; /*!< Size = 81920 (0x14000) */

/* =========================================================================================================================== */
/* ================ R_CRC ================ */
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h
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Expand Up @@ -199,7 +199,7 @@
#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3F1)

#define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x0FU)
#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU)
#define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU)

#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U)
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h
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Expand Up @@ -235,7 +235,7 @@
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13DFF3U)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FDFF3)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
#define BSP_FEATURE_LPM_HAS_STCONR (0U)
Expand Down
4 changes: 2 additions & 2 deletions ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h
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Expand Up @@ -201,7 +201,7 @@
#define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (64U)
#define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (4U)
#define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1)
#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1)
#define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_HP_VERSION (40U)
#define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0) // Feature not available on this MCU
#define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0) // Feature not available on this MCU
Expand Down Expand Up @@ -236,7 +236,7 @@
#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU)
#define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU)
#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U)
#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U)
#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U)
#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U)
#define BSP_FEATURE_LPM_HAS_STCONR (0U)
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/r_canfd/r_canfd.c
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Expand Up @@ -1053,7 +1053,7 @@ static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operati
/* Enable RX FIFOs */
for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++)
{
R_CANFD->CFDRFCC_b[i].RFE = p_global_cfg->rx_fifo_config[i] & 1U;
R_CANFD->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i];
}
}
}
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2 changes: 1 addition & 1 deletion ra/fsp/src/r_ospi/r_ospi.c
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Expand Up @@ -465,7 +465,7 @@ fsp_err_t R_OSPI_Erase (spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_addr
/* If requested byte_count is supported by underlying flash, store the command. */
if (byte_count == p_cfg->p_erase_command_list[index].size)
{
if (p_cfg_extend->memory_size == byte_count)
if (SPI_FLASH_ERASE_SIZE_CHIP_ERASE == byte_count)
{
/* Don't send address for chip erase. */
send_address = false;
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_func000.c
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Expand Up @@ -75,7 +75,7 @@ void R_SCE_func000(uint32_t *InData_PaddedMsg, int32_t MAX_CNT)
(void)OFS_ADR;
(void)MAX_CNT2;
SCE->REG_104H = 0x000000b4U;
for (iLoop = 0; iLoop < MAX_CNT; iLoop = iLoop + 16)
for (iLoop = 0; iLoop < (uint32_t)MAX_CNT; iLoop = iLoop + 16)
{
/* WAIT_LOOP */
while (1U != SCE->REG_104H_b.B31)
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2a.c
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Expand Up @@ -1177,7 +1177,7 @@ fsp_err_t R_SCE_GenerateRsa1024RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Out
}
S_RAM[0+1 + 0] = change_endian_long(SCE->REG_100H);
SCE->REG_ECH = 0x000037e9U;
for(jLoop = 0; jLoop < S_RAM[0+1]; jLoop = jLoop + 1)
for(jLoop = 0; jLoop < (int32_t)S_RAM[0+1]; jLoop = jLoop + 1)
{
SCE->REG_24H = 0x000009c0U;
/* WAIT_LOOP */
Expand Down
2 changes: 1 addition & 1 deletion ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/primitive/r_sce_p2b.c
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Expand Up @@ -1099,7 +1099,7 @@ fsp_err_t R_SCE_GenerateRsa2048RandomKeyIndexSub(uint32_t MAX_CNT, uint32_t *Out
}
S_RAM[0+1 + 0] = change_endian_long(SCE->REG_100H);
SCE->REG_ECH = 0x000037e9U;
for(jLoop = 0; jLoop < S_RAM[0+1]; jLoop = jLoop + 1)
for(jLoop = 0; jLoop < (int32_t)S_RAM[0+1]; jLoop = jLoop + 1)
{
SCE->REG_24H = 0x000009c0U;
/* WAIT_LOOP */
Expand Down
1 change: 1 addition & 0 deletions ra/fsp/src/r_sce_protected/crypto_procedures_protected/src/sce9/public/r_sce_aes.c
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Expand Up @@ -3848,6 +3848,7 @@ static fsp_err_t prepare_gcm_iv (uint8_t * initial_vector,
}
else /* if (SCE_KEY_INDEX_TYPE_AES256 == wrapped_key->type) */
{
ret = R_SCE_Aes256EncryptDecryptInitSub(&indata_cmd, wrapped_key->value, zero);
if (FSP_SUCCESS == ret)
{
R_SCE_Aes256EncryptDecryptUpdateSub(zero, hash_subkey, 4);
Expand Down
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