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plat_rcar_s4: describe non-secure DDR to optee #6

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2 changes: 1 addition & 1 deletion core/arch/arm/plat-rcar_gen4/conf.mk
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
PLATFORM_FLAVOR ?= generic_dt
PLATFORM_FLAVOR ?= spider

include core/arch/arm/cpu/cortex-armv8-0.mk

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12 changes: 0 additions & 12 deletions core/arch/arm/plat-rcar_gen4/main.c
Original file line number Diff line number Diff line change
Expand Up @@ -71,20 +71,8 @@ register_phys_mem_pgdir(DEVICE1_TYPE, DEVICE1_PA_BASE, DEVICE1_SIZE);
register_phys_mem_pgdir(DEVICE2_TYPE, DEVICE2_PA_BASE, DEVICE2_SIZE);
#endif

/* Legacy platforms */
#if defined(PLATFORM_FLAVOR_salvator_h3) || \
defined(PLATFORM_FLAVOR_salvator_h3_4x2g) || \
defined(PLATFORM_FLAVOR_salvator_m3) || \
defined(PLATFORM_FLAVOR_salvator_m3_2x4g)
register_ddr(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
register_ddr(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);
#ifdef NSEC_DDR_2_BASE
register_ddr(NSEC_DDR_2_BASE, NSEC_DDR_2_SIZE);
#endif
#ifdef NSEC_DDR_3_BASE
register_ddr(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
#endif
#endif

void console_init(void)
{
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41 changes: 3 additions & 38 deletions core/arch/arm/plat-rcar_gen4/platform_config.h
Original file line number Diff line number Diff line change
Expand Up @@ -84,45 +84,10 @@

#define MEM_SECTION_SIZE (0x00100000U)

#if defined(PLATFORM_FLAVOR_salvator_h3)
#define NSEC_DDR_0_BASE 0x47E00000
#define NSEC_DDR_0_SIZE 0x38200000
#define NSEC_DDR_1_BASE 0x500000000U
#define NSEC_DDR_1_SIZE 0x40000000
#define NSEC_DDR_2_BASE 0x600000000U
#define NSEC_DDR_2_SIZE 0x40000000
#define NSEC_DDR_3_BASE 0x700000000U
#define NSEC_DDR_3_SIZE 0x40000000

#elif defined(PLATFORM_FLAVOR_salvator_h3_4x2g)
#define NSEC_DDR_0_BASE 0x47E00000
#define NSEC_DDR_0_SIZE 0x78200000
#define NSEC_DDR_1_BASE 0x500000000U
#define NSEC_DDR_0_BASE 0x48000000
#define NSEC_DDR_0_SIZE 0x78000000
#define NSEC_DDR_1_BASE 0x480000000U
#define NSEC_DDR_1_SIZE 0x80000000U
#define NSEC_DDR_2_BASE 0x600000000U
#define NSEC_DDR_2_SIZE 0x80000000U
#define NSEC_DDR_3_BASE 0x700000000U
#define NSEC_DDR_3_SIZE 0x80000000U

#elif defined(PLATFORM_FLAVOR_salvator_m3)
#define NSEC_DDR_0_BASE 0x47E00000
#define NSEC_DDR_0_SIZE 0x78200000
#define NSEC_DDR_1_BASE 0x600000000U
#define NSEC_DDR_1_SIZE 0x80000000U

#elif defined(PLATFORM_FLAVOR_salvator_m3_2x4g)
#define NSEC_DDR_0_BASE 0x47E00000
#define NSEC_DDR_0_SIZE 0x78200000
#define NSEC_DDR_1_BASE 0x400000000U
#define NSEC_DDR_1_SIZE 0x80000000U
#define NSEC_DDR_2_BASE 0x600000000U
#define NSEC_DDR_2_SIZE 0x100000000U

#else

/* Generic DT-based platform */

#endif

#define DEVICE1_PA_BASE ROUNDDOWN(CE_BASE, CORE_MMU_PGDIR_SIZE)
#define DEVICE1_SIZE (MEM_SECTION_SIZE * 2)
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