Another attempt to fix FPGA job. 4 macro ROMs do not fit, so just dis… #120
rejunityArtifacts
Produced during runtime
| Name | Size | |
|---|---|---|
|
GDS_logs
|
301 MB |
|
|
gatelevel_test_vcd
|
8.98 MB |
|
|
gds_render
|
4.42 MB |
|
|
precheck_reports
|
6.13 KB |
|
|
tt_submission
|
103 MB |
|