完全移除 riscv 启动流程部分的汇编文件

.vscode/settings.json

@@ -2,5 +2,6 @@
     "files.associations": {
         "unistd.h": "c",
         "time.h": "c"
-    }
-}
+    },
+    "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
+}

drivers/Cargo.toml

@@ -24,9 +24,20 @@ bitmap-allocator = { git = "https://github.com/rcore-os/bitmap-allocator", rev =
 pci = { git = "https://github.com/rcore-os/pci-rs", rev = "a4e7cea6" }
 virtio-drivers = { git = "https://github.com/rcore-os/virtio-drivers", rev = "2aaf7d6", optional = true }
 rcore-console = { git = "https://github.com/rcore-os/rcore-console", default-features = false, rev = "ca5b1bc", optional = true }
-lock = { git = "https://github.com/DeathWish5/kernel-sync" }
+lock = { git = "https://github.com/DeathWish5/kernel-sync", rev = "01b2e70" }
 # smoltcp = { git = "https://github.com/smoltcp-rs/smoltcp", rev = "35e833e3", default-features = false, features = ["log", "alloc", "verbose", "proto-ipv4", "proto-ipv6", "proto-igmp", "medium-ip", "medium-ethernet", "socket-raw", "socket-udp", "socket-tcp", "socket-icmp"] }
-smoltcp = { git = "https://gitee.com/gcyyfun/smoltcp", rev="043eb60", default-features = false, features = ["alloc","log", "async", "medium-ethernet","proto-ipv4", "proto-igmp", "socket-icmp", "socket-udp", "socket-tcp", "socket-raw"] }
+smoltcp = { git = "https://gitee.com/gcyyfun/smoltcp", rev = "043eb60", default-features = false, features = [
+    "alloc",
+    "log",
+    "async",
+    "medium-ethernet",
+    "proto-ipv4",
+    "proto-igmp",
+    "socket-icmp",
+    "socket-udp",
+    "socket-tcp",
+    "socket-raw",
+] }
 
 # LibOS mode
 [target.'cfg(not(target_os = "none"))'.dependencies]
@@ -43,4 +54,6 @@ x2apic = "0.4"
 x86_64 = "0.14"
 
 [target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
-riscv = { git = "https://github.com/rust-embedded/riscv", rev = "cd31989", features = ["inline-asm"] }
+riscv = { git = "https://github.com/rust-embedded/riscv", rev = "cd31989", features = [
+    "inline-asm",
+] }

kernel-hal/Cargo.toml

@@ -1,7 +1,10 @@
 [package]
 name = "kernel-hal"
 version = "0.1.0"
-authors = ["Runji Wang <[email protected]>", "Yuekai Jia <[email protected]>"]
+authors = [
+    "Runji Wang <[email protected]>",
+    "Yuekai Jia <[email protected]>",
+]
 edition = "2018"
 description = "Kernel HAL interface definations."
 
@@ -10,7 +13,13 @@ description = "Kernel HAL interface definations."
 [features]
 default = ["libos"]
 smp = []
-libos = ["nix", "tempfile", "async-std", "bitmap-allocator", "zcore-drivers/mock"]
+libos = [
+    "nix",
+    "tempfile",
+    "async-std",
+    "bitmap-allocator",
+    "zcore-drivers/mock",
+]
 graphic = ["zcore-drivers/graphic"]
 
 loopback = []
@@ -25,8 +34,19 @@ git-version = "0.3"
 numeric-enum-macro = "0.2"
 lazy_static = { version = "1.4", features = ["spin_no_std"] }
 zcore-drivers = { path = "../drivers", features = ["virtio"] }
-lock = { git = "https://github.com/DeathWish5/kernel-sync" }
-smoltcp = { git = "https://gitee.com/gcyyfun/smoltcp", rev="043eb60", default-features = false, features = ["alloc","log", "async", "medium-ethernet","proto-ipv4", "proto-igmp", "socket-icmp", "socket-udp", "socket-tcp", "socket-raw"] }
+lock = { git = "https://github.com/DeathWish5/kernel-sync", rev = "01b2e70" }
+smoltcp = { git = "https://gitee.com/gcyyfun/smoltcp", rev = "043eb60", default-features = false, features = [
+    "alloc",
+    "log",
+    "async",
+    "medium-ethernet",
+    "proto-ipv4",
+    "proto-igmp",
+    "socket-icmp",
+    "socket-udp",
+    "socket-tcp",
+    "socket-raw",
+] }
 
 # LibOS mode
 [target.'cfg(not(target_os = "none"))'.dependencies]
@@ -53,4 +73,6 @@ x86-smpboot = { git = "https://github.com/rcore-os/x86-smpboot", rev = "1069df3"
 
 # Bare-metal mode on riscv64
 [target.'cfg(all(target_os = "none", target_arch = "riscv64"))'.dependencies]
-riscv = { git = "https://github.com/rust-embedded/riscv", rev = "cd31989", features = ["inline-asm"] }
+riscv = { git = "https://github.com/rust-embedded/riscv", rev = "cd31989", features = [
+    "inline-asm",
+] }

linux-object/Cargo.toml

@@ -38,7 +38,7 @@ smoltcp = { git = "https://gitee.com/gcyyfun/smoltcp", rev = "043eb60", default-
     "socket-raw",
 ] }
 zcore-drivers = { path = "../drivers", features = ["virtio"] }
-lock = { git = "https://github.com/DeathWish5/kernel-sync" }
+lock = { git = "https://github.com/DeathWish5/kernel-sync", rev = "01b2e70" }
 
 # LibOS mode
 [target.'cfg(not(target_os = "none"))'.dependencies]

linux-syscall/Cargo.toml

@@ -19,8 +19,11 @@ kernel-hal = { path = "../kernel-hal", default-features = false }
 rcore-fs = { git = "https://github.com/rcore-os/rcore-fs", rev = "1a3246b" }
 lazy_static = { version = "1.4", features = ["spin_no_std"] }
 bitvec = { version = "0.22", default-features = false, features = ["alloc"] }
-lock = { git = "https://github.com/DeathWish5/kernel-sync" }
-futures = { version = "0.3", default-features = false, features = ["alloc", "async-await"] }
+lock = { git = "https://github.com/DeathWish5/kernel-sync", rev = "01b2e70" }
+futures = { version = "0.3", default-features = false, features = [
+    "alloc",
+    "async-await",
+] }
 
 [dev-dependencies]
 async-std = { version = "1.10", features = ["unstable"] }
@@ -29,4 +32,4 @@ async-std = { version = "1.10", features = ["unstable"] }
 [target.'cfg(not(target_os = "none"))'.dependencies]
 
 # Bare-metal mode
-[target.'cfg(target_os = "none")'.dependencies]
+[target.'cfg(target_os = "none")'.dependencies]

zCore/Cargo.toml

@@ -64,7 +64,7 @@ zircon-object = { path = "../zircon-object" }
 linux-object = { path = "../linux-object", optional = true }
 rcore-fs = { git = "https://github.com/rcore-os/rcore-fs", rev = "1a3246b", optional = true }
 rcore-fs-sfs = { git = "https://github.com/rcore-os/rcore-fs", rev = "1a3246b", optional = true }
-lock = { git = "https://github.com/DeathWish5/kernel-sync" }
+lock = { git = "https://github.com/DeathWish5/kernel-sync", rev = "01b2e70" }
 executor = { git = "https://github.com/DeathWish5/PreemptiveScheduler", rev = "56ac2f6" }
 
 # LibOS mode
@@ -79,6 +79,7 @@ buddy_system_allocator = "0.8"
 
 # RISC-V
 [target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
+r0 = "1"
 riscv = { git = "https://github.com/rust-embedded/riscv", rev = "cd31989", features = [
     "inline-asm",
 ] }

zCore/src/handler.rs

@@ -18,9 +18,6 @@ impl KernelHandler for ZcoreKernelHandler {
     }
 
     fn handle_page_fault(&self, fault_vaddr: usize, access_flags: MMUFlags) {
-        panic!(
-            "page fault from kernel mode @ {:#x}({:?})",
-            fault_vaddr, access_flags
-        );
+        panic!("page fault from kernel mode @ {fault_vaddr:#x}({access_flags:?})");
     }
 }

zCore/src/lang.rs

@@ -7,8 +7,8 @@ use log::*;
 #[panic_handler]
 fn panic(info: &PanicInfo) -> ! {
     println!("\n\npanic cpu={}", kernel_hal::cpu::cpu_id());
-    println!("\n\n{}", info);
-    error!("\n\n{}", info);
+    println!("\n\n{info}");
+    error!("\n\n{info}");
 
     if cfg!(feature = "baremetal-test") {
         kernel_hal::cpu::reset();

zCore/src/logging.rs

@@ -13,25 +13,24 @@ pub fn set_max_level(level: &str) {
     log::set_max_level(level.parse().unwrap_or(LevelFilter::Warn));
 }
 
+#[inline]
 pub fn print(args: fmt::Arguments) {
     kernel_hal::console::console_write_fmt(args);
 }
 
 #[macro_export]
 macro_rules! print {
-    ($($arg:tt)*) => ({
-        $crate::logging::print(format_args!($($arg)*));
-    });
+    ($($arg:tt)*) => ($crate::logging::print(core::format_args!($($arg)*)));
 }
 
 #[macro_export]
 macro_rules! println {
-    ($fmt:expr) => (print!(concat!($fmt, "\n")));
-    ($fmt:expr, $($arg:tt)*) => (print!(concat!($fmt, "\n"), $($arg)*));
+    () => ($crate::print!("\n"));
+    ($($arg:tt)*) => ($crate::logging::print(core::format_args_nl!($($arg)*)));
 }
 
-#[repr(u8)]
 #[allow(dead_code)]
+#[repr(u8)]
 enum ColorCode {
     Black = 30,
     Red = 31,
@@ -94,21 +93,21 @@ impl Log for SimpleLogger {
         };
         print(with_color!(
             ColorCode::White,
-            "[{} {} {} {}\n",
-            {
+            "[{time} {level} {info} {data}\n",
+            time = {
                 cfg_if! {
                     if #[cfg(feature = "libos")] {
                         use chrono::{TimeZone, Local};
                         Local.timestamp_nanos(now.as_nanos() as _).format("%Y-%m-%d %H:%M:%S%.6f")
                     } else {
                         let micros = now.as_micros();
-                        format_args!("{:>3}.{:06}", micros / 1_000_000, micros % 1_000_000)
+                        format_args!("{s:>3}.{us:06}", s = micros / 1_000_000, us = micros % 1_000_000)
                     }
                 }
             },
-            with_color!(level_color, "{:<5}", level),
-            with_color!(ColorCode::White, "{} {}:{} {}]", cpu_id, pid, tid, target),
-            with_color!(args_color, "{}", record.args()),
+            level = with_color!(level_color, "{level:<5}"),
+            info = with_color!(ColorCode::White, "{cpu_id} {pid}:{tid} {target}]"),
+            data = with_color!(args_color, "{args}", args = record.args()),
         ));
     }
 

zCore/src/main.rs

@@ -2,6 +2,8 @@
 #![cfg_attr(not(feature = "libos"), no_std)]
 #![feature(lang_items)]
 #![feature(core_intrinsics)]
+#![feature(naked_functions, asm_sym, asm_const)]
+#![feature(format_args_nl)]
 #![deny(warnings)]
 
 use core::sync::atomic::{AtomicBool, Ordering};

zCore/src/memory.rs

@@ -29,7 +29,7 @@ fn frame_idx_to_phys_addr(idx: usize) -> PhysAddr {
 }
 
 pub fn init_frame_allocator(regions: &[Range<PhysAddr>]) {
-    debug!("init_frame_allocator regions: {:x?}", regions);
+    debug!("init_frame_allocator regions: {regions:x?}");
     let mut ba = FRAME_ALLOCATOR.lock();
     for region in regions {
         let frame_start = phys_addr_to_frame_idx(region.start);
@@ -47,7 +47,7 @@ pub fn init_frame_allocator(regions: &[Range<PhysAddr>]) {
 
 pub fn frame_alloc() -> Option<PhysAddr> {
     let ret = FRAME_ALLOCATOR.lock().alloc().map(frame_idx_to_phys_addr);
-    trace!("frame_alloc(): {:x?}", ret);
+    trace!("frame_alloc(): {ret:x?}");
     ret
 }
 
@@ -57,16 +57,14 @@ pub fn frame_alloc_contiguous(frame_count: usize, align_log2: usize) -> Option<P
         .alloc_contiguous(frame_count, align_log2)
         .map(frame_idx_to_phys_addr);
     trace!(
-        "frame_alloc_contiguous(): {:x?} ~ {:x?}, align_log2={}",
-        ret,
-        ret.map(|x| x + frame_count),
-        align_log2,
+        "frame_alloc_contiguous(): {ret:x?} ~ {end_ret:x?}, align_log2={align_log2}",
+        end_ret = ret.map(|x| x + frame_count),
     );
     ret
 }
 
 pub fn frame_dealloc(target: PhysAddr) {
-    trace!("frame_dealloc(): {:x}", target);
+    trace!("frame_dealloc(): {target:x}");
     FRAME_ALLOCATOR
         .lock()
         .dealloc(phys_addr_to_frame_idx(target))

zCore/src/platform/libos/mod.rs

@@ -0,0 +1,3 @@
+mod entry;
+
+pub mod consts;

zCore/src/platform/mod.rs

@@ -1,18 +1,14 @@
 cfg_if! {
     if #[cfg(feature = "libos")] {
-        #[path = "libos/entry.rs"]
-        mod entry;
-        #[path = "libos/consts.rs"]
-        pub mod consts;
+        #[path = "libos/mod.rs"]
+        mod arch;
     } else if #[cfg(target_arch = "x86_64")] {
-        #[path = "x86/entry.rs"]
-        mod entry;
-        #[path = "x86/consts.rs"]
-        pub mod consts;
+        #[path = "x86/mod.rs"]
+        mod arch;
     } else if #[cfg(target_arch = "riscv64")] {
-        #[path = "riscv/entry.rs"]
-        mod entry;
-        #[path = "riscv/consts.rs"]
-        pub mod consts;
+        #[path = "riscv/mod.rs"]
+        mod arch;
     }
 }
+
+pub use arch::consts;