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Fix: Make cached gate an argument for PackedInstruction::new()- Bri…
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…ng back deleted cached gates.
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@raynelfss
raynelfss committed Dec 11, 2024
1 parent 84def52 commit 82f6cc6
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Showing 6 changed files with 53 additions and 4 deletions.
10 changes: 10 additions & 0 deletions crates/accelerate/src/twirling.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -208,6 +208,8 @@ fn twirl_gate(
circ.cargs_interner().get_default(),
None,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
std::sync::OnceLock::new(),
),
)?;
out_circ.push(
Expand All @@ -218,6 +220,8 @@ fn twirl_gate(
circ.cargs_interner().get_default(),
None,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
std::sync::OnceLock::new(),
),
)?;

Expand All @@ -230,6 +234,8 @@ fn twirl_gate(
circ.cargs_interner().get_default(),
None,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
std::sync::OnceLock::new(),
),
)?;
out_circ.push(
Expand All @@ -240,6 +246,8 @@ fn twirl_gate(
circ.cargs_interner().get_default(),
None,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
std::sync::OnceLock::new(),
),
)?;

Expand Down Expand Up @@ -352,6 +360,8 @@ fn generate_twirled_circuit(
.collect::<SmallVec<[Param; 3]>>(),
),
inst.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
std::sync::OnceLock::new(),
);
out_circ.push(py, new_inst)?;
} else {
Expand Down
4 changes: 4 additions & 0 deletions crates/accelerate/src/unitary_synthesis.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,8 @@ fn apply_synth_sequence(
out_dag.cargs_interner.get_default(),
new_params,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
);
instructions.push(instruction);
}
Expand Down Expand Up @@ -281,6 +283,8 @@ fn py_run_main_loop(
packed_instr.clbits(),
(!new_node_op.params.is_empty()).then_some(new_node_op.params),
new_node_op.extra_attrs,
#[cfg(feature = "cache_pygates")]
new_node.unbind().into(),
);
}
if !(packed_instr.op().name() == "unitary"
Expand Down
14 changes: 14 additions & 0 deletions crates/circuit/src/circuit_data.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -301,6 +301,8 @@ impl CircuitData {
inst.clbits(),
(!inst.params_view().is_empty()).then_some(inst.params_view().into()),
inst.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
));
}
} else if copy_instructions {
Expand All @@ -311,6 +313,8 @@ impl CircuitData {
inst.clbits(),
(!inst.params_view().is_empty()).then_some(inst.params_view().into()),
inst.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
));
}
} else {
Expand Down Expand Up @@ -690,6 +694,8 @@ impl CircuitData {
clbits_id,
(!inst.params_view().is_empty()).then_some(inst.params_view().into()),
inst.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
inst.py_op.clone(),
));
self.track_instruction_parameters(py, new_index)?;
}
Expand Down Expand Up @@ -937,6 +943,8 @@ impl CircuitData {
clbits,
params,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
));
res.track_instruction_parameters(py, res.data.len() - 1)?;
}
Expand Down Expand Up @@ -1044,6 +1052,8 @@ impl CircuitData {
no_clbit_index,
params,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
));
res.track_instruction_parameters(py, res.data.len() - 1)?;
}
Expand Down Expand Up @@ -1100,6 +1110,8 @@ impl CircuitData {
no_clbit_index,
params,
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
));
Ok(())
}
Expand Down Expand Up @@ -1194,6 +1206,8 @@ impl CircuitData {
clbits,
(!inst.params.is_empty()).then_some(inst.params.clone()),
inst.extra_attrs.clone(),
#[cfg(feature = "cache_pygates")]
inst.py_op.clone(),
))
}

Expand Down
2 changes: 2 additions & 0 deletions crates/circuit/src/converters.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,8 @@ pub fn dag_to_circuit(
.collect(),
),
instr.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
))
} else {
Ok(instr.clone())
Expand Down
18 changes: 18 additions & 0 deletions crates/circuit/src/dag_circuit.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1768,6 +1768,8 @@ def _format(operand):
clbits_id,
(!py_op.params.is_empty()).then_some(py_op.params),
py_op.extra_attrs,
#[cfg(feature = "cache_pygates")]
op.unbind().into(),
);

if check {
Expand Down Expand Up @@ -1820,6 +1822,8 @@ def _format(operand):
clbits_id,
(!py_op.params.is_empty()).then_some(py_op.params),
py_op.extra_attrs,
#[cfg(feature = "cache_pygates")]
op.unbind().into(),
);

if check {
Expand Down Expand Up @@ -5119,6 +5123,8 @@ impl DAGCircuit {
self.cargs_interner.insert(cargs),
params,
extra_attrs,
#[cfg(feature = "cache_pygates")]
py_op,
);

if front {
Expand Down Expand Up @@ -5559,6 +5565,8 @@ impl DAGCircuit {
clbits,
params,
op_node.instruction.extra_attrs.clone(),
#[cfg(feature = "cache_pygates")]
op_node.instruction.py_op.clone(),
);
NodeType::Operation(inst)
} else {
Expand Down Expand Up @@ -6156,6 +6164,8 @@ impl DAGCircuit {
(!new_gate.1.is_empty())
.then_some(new_gate.1.iter().map(|x| Param::Float(*x)).collect()),
ExtraInstructionAttributes::default(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
)
} else {
panic!("This method only works if provided index is an op node");
Expand Down Expand Up @@ -6251,6 +6261,8 @@ impl DAGCircuit {
self.cargs_interner.get_default(),
(!new_op.params.is_empty()).then_some(new_op.params),
new_op.extra_attrs,
#[cfg(feature = "cache_pygates")]
py_op,
);
let new_index = self.dag.add_node(NodeType::Operation(inst));
self.dag.add_edge(source, new_index, weight.clone());
Expand Down Expand Up @@ -6690,6 +6702,8 @@ impl DAGCircuit {
new_cargs,
(!instr.params_view().is_empty()).then_some(instr.params_view().into()),
instr.extra_attrs().clone(),
#[cfg(feature = "cache_pygates")]
OnceLock::new(),
))
})
.collect::<PyResult<Vec<_>>>()?;
Expand Down Expand Up @@ -6822,6 +6836,8 @@ impl DAGCircuit {
clbits,
(!py_op.params.is_empty()).then_some(py_op.params),
py_op.extra_attrs,
#[cfg(feature = "cache_pygates")]
op.unbind().into(),
));

let new_node = self
Expand Down Expand Up @@ -6942,6 +6958,8 @@ impl DAGCircuit {
old_packed.clbits(),
(!new_op.params.is_empty()).then_some(new_op.params),
extra_attrs,
#[cfg(feature = "cache_pygates")]
py_op_cache.map(OnceLock::from).unwrap_or_default(),
));
if let Some(weight) = self.dag.node_weight_mut(node_index) {
*weight = new_weight;
Expand Down
9 changes: 5 additions & 4 deletions crates/circuit/src/packed_instruction.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -525,6 +525,7 @@ impl PackedInstruction {
clbits: Interned<[Clbit]>,
params: Option<SmallVec<[Param; 3]>>,
extra_attrs: ExtraInstructionAttributes,
#[cfg(feature = "cache_pygates")] py_op: OnceLock<PyObject>,
) -> Self {
Self {
op,
Expand All @@ -533,7 +534,7 @@ impl PackedInstruction {
params: params.map(Box::new),
extra_attrs,
#[cfg(feature = "cache_pygates")]
py_op: OnceLock::new(),
py_op,
}
}

Expand Down Expand Up @@ -567,7 +568,7 @@ impl PackedInstruction {

// Setters

/// Retrieves an immutable reference to the instruction's underlying operation.
/// Retrieves a mutable reference to the instruction's underlying operation.
pub fn op_mut(&mut self) -> &mut PackedOperation {
#[cfg(feature = "cache_pygates")]
{
Expand All @@ -576,12 +577,12 @@ impl PackedInstruction {
&mut self.op
}

/// Retrieves an immutable reference to the index under which the interner has stored `qubits`.
/// Retrieves a mutable reference to the index under which the interner has stored `qubits`.
pub fn qubits_mut(&mut self) -> &mut Interned<[Qubit]> {
&mut self.qubits
}

/// Retrieves an immutable reference to the index under which the interner has stored `clbits`.
/// Retrieves a mutable reference to the index under which the interner has stored `clbits`.
pub fn clbits_mut(&mut self) -> &mut Interned<[Clbit]> {
&mut self.clbits
}
Expand Down

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