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FIC-486-GAC-2 Cache Module reproduction

Reverse Engineered non standard 256K L2 Cache Module for use in:

Potentially also:

  • AT&T Globalyst 520 = NCR 3238 = FIC 486-PAK-3 needs confirmation
  • NCR 3231 ?
  • AT&T Globalyst 525 = NCR 3253 ?

Incompatible platforms also reusing VLB slot for Cache:

Resources

Original DOC: 13630 ASSY: 008-0078204 A Cache module:

rev 2 front

rev 2.1 front , back

plugged into FIC 486-GAC-2


Vogons FIC 486-GAC-2 and proprietary cache module thread:

majestyk: "FIC sold two different versions with different pinouts (and the same "VLB"-socket). Only the one in the pictures works on a 486-GAC2 and a few other FIC mainboards."

This project was only possible with help provided by majestyk - owner of this very rare Cache module, and RockstarRunner - FIC 486-GAC-2 owner looking for said Cache module. Huge thanks for taking time to capture high resolution pictures and validating progress with measurements.

UMC UM61256A 32K x 8 Static RAM datasheet

VESA VLB slot pinout VESA VLB slot dimensions

Progress report

3/23/2024: Final Rev 2.4. Reworked SRAM footprint for easier hand soldering, slightly optimized capacitor placement.

2/29/2024: Final Rev 2.3. Slightly thicker tracks and silkscreen text, additional clearance work. Shrank from initial prototype, should be almost the height of original. Height when inserted 26.3mm, height including slot 33.6mm.

2/28/2024: Prototypes assembled, didnt work at first try. Turns out I swapped few power/ground pins in the connector resulting in dead short. Great sleuthing by miisalo uncovered thia mishap, after cutting bad connections we have sucessfull boot.

2/27/2024: Prototypes arrived. Who can spot the problem?

Will require some finessing with sandpaper to uncover edge slot pads :)

2/11/2024: 99% done, ERC&DRC 0 errors 0 warnings. Footprints should be correct now. Gerbers sent for manufacturing.

2/8/2024: 95% there, 0 errors, 7 Warnings. 5 connections missing, 11 guesses and assumptions on U1 U2 and some more on common lines.

2/6/2024: 90% there, 0 errors 18 warnings. Just a couple tracks left.

2/5/2024: 80% there, 0 drc errors, 62 violations. Still bad footprints and I havent gotten around to fixing power/ground pins. Whats left is figuring LS244 address buffering mapping, TAG ram address and output pins to edge mapping, WE/CE/OE mapping to edge.

2/4/2024: Very VIP, only about 50% there at the moment.

02/3/2024: Project start. Figuring out how to make edge connector footprint, searching for SOJ-28L footprint.

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