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drm/vc4: crtc: Support odd horizontal timings on BCM2712 #5679

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merged 1 commit into from
Nov 6, 2023
Merged

drm/vc4: crtc: Support odd horizontal timings on BCM2712 #5679

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12 changes: 4 additions & 8 deletions drivers/gpu/drm/vc4/vc4_crtc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -398,12 +398,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode

vc4_crtc_pixelvalve_reset(crtc);

/*
* NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
* bit that, when set, will allow to specify the timings in
* pixels instead of cycles, thus allowing to specify odd
* timings.
*/
CRTC_WRITE(PV_HORZA,
VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
PV_HORZA_HBP) |
Expand Down Expand Up @@ -448,6 +442,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
*/
CRTC_WRITE(PV_V_CONTROL,
PV_VCONTROL_CONTINUOUS |
(vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
(is_dsi ? PV_VCONTROL_DSI : 0) |
PV_VCONTROL_INTERLACE |
(odd_field_first
Expand All @@ -459,6 +454,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
} else {
CRTC_WRITE(PV_V_CONTROL,
PV_VCONTROL_CONTINUOUS |
(vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
(is_dsi ? PV_VCONTROL_DSI : 0));
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
}
Expand Down Expand Up @@ -1332,7 +1328,7 @@ const struct vc4_pv_data bcm2712_pv0_data = {
.hvs_output = 0,
},
.fifo_depth = 64,
.pixels_per_clock = 2,
.pixels_per_clock = 1,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_HDMI0,
},
Expand All @@ -1345,7 +1341,7 @@ const struct vc4_pv_data bcm2712_pv1_data = {
.hvs_output = 1,
},
.fifo_depth = 64,
.pixels_per_clock = 2,
.pixels_per_clock = 1,
.encoder_types = {
[0] = VC4_ENCODER_TYPE_HDMI1,
},
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/vc4/vc4_hdmi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3958,7 +3958,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
PHY_LANE_2,
PHY_LANE_CK,
},
.unsupported_odd_h_timings = true,
.unsupported_odd_h_timings = false,
.external_irq_controller = true,

.init_resources = vc5_hdmi_init_resources,
Expand All @@ -3985,7 +3985,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
PHY_LANE_2,
PHY_LANE_CK,
},
.unsupported_odd_h_timings = true,
.unsupported_odd_h_timings = false,
.external_irq_controller = true,

.init_resources = vc5_hdmi_init_resources,
Expand Down
1 change: 1 addition & 0 deletions drivers/gpu/drm/vc4/vc4_regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -155,6 +155,7 @@
# define PV_CONTROL_EN BIT(0)

#define PV_V_CONTROL 0x04
# define PV_VCONTROL_ODD_TIMING BIT(29)
# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
# define PV_VCONTROL_ODD_DELAY_SHIFT 6
# define PV_VCONTROL_ODD_FIRST BIT(5)
Expand Down