refactor(tapac): add test to tapa.verilog.xilinx.module

.bazelrc

@@ -3,6 +3,7 @@ build --copt=-Wno-unknown-pragmas
 build --copt=-Wno-unused-label
 build --copt=-Werror
 build --incompatible_autoload_externally=+@rules_python,+@rules_shell
+build --incompatible_default_to_explicit_init_py # Don't overwrite __init__.py files
 build --incompatible_strict_action_env
 
 build:asan --compilation_mode=dbg

bazel/BUILD.bazel

@@ -27,7 +27,10 @@ string_flag(
     ],
 )
 
-exports_files(["nuitka_wrapper.py"])
+exports_files([
+    "nuitka_wrapper.py",
+    "pytest_wrapper.py",
+])
 
 xilinx_wrapper(
     name = "v++",

bazel/pytest_rules.bzl

@@ -0,0 +1,18 @@
+"""Custom rule to test Python modules with pytest."""
+
+# Copyright (c) 2025 RapidStream Design Automation, Inc. and contributors.
+# All rights reserved. The contributor(s) of this file has/have agreed to the
+# RapidStream Contributor License Agreement.
+
+load("@rules_python//python:defs.bzl", _py_test = "py_test")
+load("@tapa_deps//:requirements.bzl", "requirement")
+
+def py_test(name, srcs, deps = [], args = [], **kwargs):
+    _py_test(
+        name = name,
+        main = "//bazel:pytest_wrapper.py",
+        srcs = srcs + ["//bazel:pytest_wrapper.py"],
+        deps = deps + [requirement("pytest")],
+        args = args + ["$(location %s)" % x for x in srcs],
+        **kwargs
+    )

bazel/pytest_wrapper.py

@@ -0,0 +1,12 @@
+import sys
+
+import pytest
+
+__copyright__ = """
+Copyright (c) 2025 RapidStream Design Automation, Inc. and contributors.
+All rights reserved. The contributor(s) of this file has/have agreed to the
+RapidStream Contributor License Agreement.
+"""
+
+if __name__ == "__main__":
+    sys.exit(pytest.main(sys.argv[1:]))

tapa/BUILD.bazel

@@ -94,6 +94,7 @@ py_library(
         ":util",
         "//tapa/backend",
         "//tapa/verilog",
+        "//tapa/verilog/xilinx:module",
         requirement("psutil"),
         requirement("pyverilog"),
         requirement("pyyaml"),

tapa/requirements.in

@@ -3,6 +3,7 @@ coloredlogs
 jinja2
 nuitka
 psutil
+pytest
 pyverilog
 pyyaml
 toposort

tapa/requirements_lock.txt

@@ -16,6 +16,10 @@ humanfriendly==10.0 \
     --hash=sha256:1697e1a8a8f550fd43c2865cd84542fc175a61dcb779b6fee18cf6b6ccba1477 \
     --hash=sha256:6b0b831ce8f15f7300721aa49829fc4e83921a9a301cc7f606be6686a2288ddc
     # via coloredlogs
+iniconfig==2.0.0 \
+    --hash=sha256:2d91e135bf72d31a410b17c16da610a82cb55f6b0477d1a902134b24a455b8b3 \
+    --hash=sha256:b6a85871a79d2e3b22d2d1b94ac2824226a63c6b741c88f7ae975f18b6778374
+    # via pytest
 jinja2==3.1.5 \
     --hash=sha256:8fefff8dc3034e27bb80d67c671eb8a9bc424c0ef4c0826edbff304cceff43bb \
     --hash=sha256:aba0f4dc9ed8013c424088f68a5c226f7d6097ed89b246d7749c2ec4175c6adb
@@ -92,6 +96,14 @@ ordered-set==4.1.0 \
     --hash=sha256:046e1132c71fcf3330438a539928932caf51ddbc582496833e23de611de14562 \
     --hash=sha256:694a8e44c87657c59292ede72891eb91d34131f6531463aab3009191c77364a8
     # via nuitka
+packaging==24.2 \
+    --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 \
+    --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f
+    # via pytest
+pluggy==1.5.0 \
+    --hash=sha256:2cffa88e94fdc978c4c574f15f9e59b7f4201d439195c3715ca9e2486f1d0cf1 \
+    --hash=sha256:44e1ad92c8ca002de6377e165f3e0f1be63266ab4d554740532335b9d75ea669
+    # via pytest
 ply==3.11 \
     --hash=sha256:00c7c1aaa88358b9c765b6d3000c6eec0ba42abca5351b095321aef446081da3 \
     --hash=sha256:096f9b8350b65ebd2fd1346b12452efe5b9607f7482813ffca50c22722a807ce
@@ -115,6 +127,10 @@ psutil==6.1.1 \
     --hash=sha256:f35cfccb065fff93529d2afb4a2e89e363fe63ca1e4a5da22b603a85833c2649 \
     --hash=sha256:fc0ed7fe2231a444fc219b9c42d0376e0a9a1a72f16c5cfa0f68d19f1a0663e8
     # via -r tapa/requirements.in
+pytest==8.3.4 \
+    --hash=sha256:50e16d954148559c9a74109af1eaf0c945ba2d8f30f0a3d3335edde19788b6f6 \
+    --hash=sha256:965370d062bce11e73868e0335abac31b4d3de0e82f4007408d242b4f8610761
+    # via -r tapa/requirements.in
 pyverilog==1.3.0 \
     --hash=sha256:59d93e9004ebe9e713e2fd6a9784a09e2d6b3c098091fd367795eb20329ae4a8
     # via -r tapa/requirements.in

tapa/verilog/BUILD.bazel

@@ -11,6 +11,7 @@ py_library(
     srcs = glob(["*.py"]),
     visibility = ["//tapa:__subpackages__"],
     deps = [
+        "//tapa:util",
         "//tapa/backend",
         "//tapa/verilog/xilinx",
         requirement("jinja2"),

tapa/verilog/xilinx/BUILD.bazel

@@ -5,6 +5,7 @@
 # RapidStream Contributor License Agreement.
 
 load("@tapa_deps//:requirements.bzl", "requirement")
+load("//bazel:pytest_rules.bzl", "py_test")
 
 package(
     default_visibility = ["//tapa:__subpackages__"],
@@ -14,10 +15,33 @@ py_library(
     name = "xilinx",
     srcs = glob(
         ["*.py"],
+        exclude = [
+            "module.py",
+            "*_test.py",
+        ],
     ),
     deps = [
         "//tapa/backend",
         requirement("jinja2"),
         requirement("pyverilog"),
     ],
 )
+
+py_library(
+    name = "module",
+    srcs = ["module.py"],
+    deps = [
+        "//tapa/backend",
+        "//tapa/verilog",
+        requirement("jinja2"),
+        requirement("pyverilog"),
+    ],
+)
+
+py_test(
+    name = "module_test",
+    srcs = ["module_test.py"],
+    deps = [
+        ":module",
+    ],
+)

tapa/verilog/xilinx/module_test.py

@@ -0,0 +1,28 @@
+"""Unit tests for tapa.verilog.xilinx.module."""
+
+__copyright__ = """
+Copyright (c) 2025 RapidStream Design Automation, Inc. and contributors.
+All rights reserved. The contributor(s) of this file has/have agreed to the
+RapidStream Contributor License Agreement.
+"""
+
+import pytest
+
+from tapa.verilog.xilinx.module import Module
+
+
+def test_invalid_module() -> None:
+    with pytest.raises(ValueError, match="`files` and `name` cannot both be empty"):
+        Module()
+
+
+def test_empty_module() -> None:
+    """An empty module can be constructed from a name.
+
+    This is used to create placeholders before Verilog is parsed, and to create
+    skeleton FSM modules.
+    """
+    module = Module(name="foo")
+
+    assert module.name == "foo"
+    assert not module.ports