fix incorrect ainneg

quartiq · Jul 7, 2023 · 86c976b · 86c976b
1 parent 4fecade
commit 86c976b
Showing 1 changed file with 13 additions and 1 deletion.
diff --git a/src/hardware/ad7172.rs b/src/hardware/ad7172.rs
@@ -133,7 +133,19 @@ pub mod Channel {
         pub const REF_P: u32 = 0b10101 << 5;
         pub const REF_N: u32 = 0b10110 << 5;
     }
-    pub use Ainpos as Ainneg;
+    pub mod Ainneg {
+        pub const AIN0: u32 = 0b00000;
+        pub const AIN1: u32 = 0b00001;
+        pub const AIN2: u32 = 0b00010;
+        pub const AIN3: u32 = 0b00011;
+        pub const AIN4: u32 = 0b00100;
+        pub const TEMPERATURESENSOR_P: u32 = 0b10001;
+        pub const TEMPERATURESENSOR_N: u32 = 0b10010;
+        pub const AVDD_MINUS_AVSS_OVER_5_P: u32 = 0b10011;
+        pub const AVDD_MINUS_AVSS_OVER_5_N: u32 = 0b10100;
+        pub const REF_P: u32 = 0b10101;
+        pub const REF_N: u32 = 0b10110;
+    }
 }
 
 /// ADC SETUPCON register settings. Valid for registers SETUPCON0-SETUPCON3.