Adding fst and struct trace support

[KelvinChung2000]

I have added support for tracing the structure correctly in the waveform

I have also added fst format to reduce the trace file size since tracing the structure increases the file size.

[KelvinChung2000]

Are there any ways to check if the metadata has changed so we can make Verilator perform a recompile? Now, if I turn the vl_trace_struct off, I must delete the obj directory to make the flag take effect.

[cbatten]

I think we write some specific metadata into a comment in the generated verilog so when we regenerate the verilog with different metadata it ends up forcing a recompile? Maybe you can see how we do this for VCD tracing? We have a way where if you turn on VCD tracing it results in forcing Verilator to do a recompile?

[yo96]

Here's where we do the check:

pymtl3/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py

Lines 340 to 347 in 4b3bc18

	# Check if the configurations from the last run are the same
	is_config_cached = False
	config_file = f'pymtl_import_config_{ip_cfg.translated_top_module}.json'
	new_cfg = s.serialize_cfg( ip_cfg )
	if os.path.exists(config_file):
	with open(config_file) as fd:
	if s.is_same_cfg( json.load( fd ), new_cfg ):
	is_config_cached = True

[KelvinChung2000]

Is the [0] after a 1-bit signal in the trace added by Verilator? Or is it coming from the RTL translation pass?

[yo96]

Is the [0] after a 1-bit signal in the trace added by Verilator? Or is it coming from the RTL translation pass?

I think it comes from the translated verilog.

[KelvinChung2000]

I want to fix that, but it will probably be in another pull request. I will open an issue and ask where to look.