[import] Fix data type declaration for signals of different widths

pymtl · Dec 7, 2023 · 7e55309 · 7e55309
1 parent 58ea59a
commit 7e55309
Showing 1 changed file with 8 additions and 5 deletions.
diff --git a/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py b/pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportPass.py
@@ -699,13 +699,16 @@ def gen_signal_decl_c( s, name, port ):
 
     c_dim = s._get_c_dim( port )
     nbits = s._get_c_nbits( port )
+
+    # According to the C++ spec, unsigned char, unsigned short, and unsigned
+    # long long have the width of 8, 16, 64 across the four most popular
+    # data models (LP32, ILP32, LLP64, LP64); unsigned long has width 32
+    # with data model LP32, ILP32, LLP64 but not LP64.
     UNSIGNED_8  = 'unsigned char'
     UNSIGNED_16 = 'unsigned short'
-    UNSIGNED_32 = 'unsigned int'
-    if sys.maxsize > 2**32:
-      UNSIGNED_64 = 'unsigned long'
-    else:
-      UNSIGNED_64 = 'unsigned long long'
+    UNSIGNED_32 = 'unsigned int' if sys.maxsize > 2**31-1 else 'unsigned long'
+    UNSIGNED_64 = 'unsigned long long'
+
     if    nbits <= 8:  data_type = UNSIGNED_8
     elif  nbits <= 16: data_type = UNSIGNED_16
     elif  nbits <= 32: data_type = UNSIGNED_32