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Clean codes, update README #11

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Nov 13, 2024
Merged

Clean codes, update README #11

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7d3af44
fix: "non-local impl definition" warning from recent nightlies
decaday Nov 13, 2024
bee8e46
feat: enable ADC CKMode config
decaday Nov 13, 2024
a878173
chore: remove unused
decaday Nov 13, 2024
13b2983
docs: update readme
decaday Nov 13, 2024
c8f567c
style: cargo fmt
decaday Nov 13, 2024
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20 changes: 14 additions & 6 deletions README.md
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Expand Up @@ -46,26 +46,34 @@ For a full list of chip capabilities and peripherals, check the [py32-data](http
| GPIO | | ✅ | | |
| INTERRUPT | | ✅ | | |
| DMA | N/A | | | |
| EXTI* | | ✅ | | |
| EXTI | | ✅+ | | |
| USART | | | | |
| I2C* | | | | |
| SPI* | | | | |
| ADC* | | ✅ | | |
| I2C | | ✅ | | |
| SPI | | | | |
| ADC | | ✅+ | | |
| RTC | | | | |
| Timer(PWM) | | ✅ | | |
| USB/OTG | N/A | N/A | | |
| USB/OTG | N/A | N/A | | |

- ✅ : Expected to work
- ❌ : Not implemented
- ❓ : Not tested
- `*` marks the async driver
- `+` : marks the async driver
- TODO: I haven't got a dev board yet, help-wanted
- N/A: Not available

### TODOs

Too many...

- DMA Support (Channel Map, Codegen, API, RingBuffer, I2C...)

- Other series

- SPI, USART

- ...

## time-driver

This crate provides an implementation of the Embassy `time-driver`.
Expand Down
174 changes: 87 additions & 87 deletions build.rs
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@@ -1,4 +1,4 @@
use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet};
use std::collections::{BTreeMap, BTreeSet, HashMap/*, HashSet*/};
use std::fmt::Write as _;
use std::io::Write;
use std::path::{Path, PathBuf};
Expand All @@ -9,7 +9,7 @@ use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
use py32_metapac::metadata::ir::BitOffset;
use py32_metapac::metadata::{
MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode,
MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, /*StopMode,*/
// ALL_CHIPS, ALL_PERIPHERAL_VERSIONS,
METADATA,
};
Expand Down Expand Up @@ -135,36 +135,36 @@ fn main() {
struct SplitFeature {
feature_name: String,
pin_name_with_c: String,
#[cfg(feature = "_split-pins-enabled")]
pin_name_without_c: String,
// #[cfg(feature = "_split-pins-enabled")]
// pin_name_without_c: String,
}

// Extra analog switch pins available on most H7 chips
let split_features: Vec<SplitFeature> = vec![
#[cfg(feature = "split-pa0")]
SplitFeature {
feature_name: "split-pa0".to_string(),
pin_name_with_c: "PA0_C".to_string(),
pin_name_without_c: "PA0".to_string(),
},
#[cfg(feature = "split-pa1")]
SplitFeature {
feature_name: "split-pa1".to_string(),
pin_name_with_c: "PA1_C".to_string(),
pin_name_without_c: "PA1".to_string(),
},
#[cfg(feature = "split-pc2")]
SplitFeature {
feature_name: "split-pc2".to_string(),
pin_name_with_c: "PC2_C".to_string(),
pin_name_without_c: "PC2".to_string(),
},
#[cfg(feature = "split-pc3")]
SplitFeature {
feature_name: "split-pc3".to_string(),
pin_name_with_c: "PC3_C".to_string(),
pin_name_without_c: "PC3".to_string(),
},
// #[cfg(feature = "split-pa0")]
// SplitFeature {
// feature_name: "split-pa0".to_string(),
// pin_name_with_c: "PA0_C".to_string(),
// pin_name_without_c: "PA0".to_string(),
// },
// #[cfg(feature = "split-pa1")]
// SplitFeature {
// feature_name: "split-pa1".to_string(),
// pin_name_with_c: "PA1_C".to_string(),
// pin_name_without_c: "PA1".to_string(),
// },
// #[cfg(feature = "split-pc2")]
// SplitFeature {
// feature_name: "split-pc2".to_string(),
// pin_name_with_c: "PC2_C".to_string(),
// pin_name_without_c: "PC2".to_string(),
// },
// #[cfg(feature = "split-pc3")]
// SplitFeature {
// feature_name: "split-pc3".to_string(),
// pin_name_with_c: "PC3_C".to_string(),
// pin_name_without_c: "PC3".to_string(),
// },
];

for split_feature in &split_features {
Expand Down Expand Up @@ -1455,18 +1455,18 @@ fn main() {
// Add the "_C" variant to the table. The solution is not optimal, though.
// Adding them only when the corresponding GPIOx also appears.
// This should avoid unintended side-effects as much as possible.
#[cfg(feature = "_split-pins-enabled")]
for split_feature in &split_features {
if split_feature.pin_name_without_c == pin_name {
pins_table.push(vec![
split_feature.pin_name_with_c.to_string(),
p.name.to_string(),
port_num.to_string(),
pin_num.to_string(),
format!("EXTI{}", pin_num),
]);
}
}
// #[cfg(feature = "_split-pins-enabled")]
// for split_feature in &split_features {
// if split_feature.pin_name_without_c == pin_name {
// pins_table.push(vec![
// split_feature.pin_name_with_c.to_string(),
// p.name.to_string(),
// port_num.to_string(),
// pin_num.to_string(),
// format!("EXTI{}", pin_num),
// ]);
// }
// }
}
}

Expand Down Expand Up @@ -1638,59 +1638,59 @@ fn main() {
// ========
// Configs for multicore and for targeting groups of chips

fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
let mut cfgs = Vec::new();
// fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
// let mut cfgs = Vec::new();

// Multicore
// // Multicore

let mut s = chip_name.split('_');
let mut chip_name: String = s.next().unwrap().to_string();
let core_name = if let Some(c) = s.next() {
if !c.starts_with("CM") {
chip_name.push('_');
chip_name.push_str(c);
None
} else {
Some(c)
}
} else {
None
};
// let mut s = chip_name.split('_');
// let mut chip_name: String = s.next().unwrap().to_string();
// let core_name = if let Some(c) = s.next() {
// if !c.starts_with("CM") {
// chip_name.push('_');
// chip_name.push_str(c);
// None
// } else {
// Some(c)
// }
// } else {
// None
// };

if let Some(core) = core_name {
cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core));
}
// if let Some(core) = core_name {
// cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core));
// }

// Configs for targeting groups of chips
if &chip_name[..8] == "stm32wba" {
cfgs.push(chip_name[..8].to_owned()); // stm32wba
cfgs.push(chip_name[..10].to_owned()); // stm32wba52
cfgs.push(format!("package_{}", &chip_name[10..11]));
cfgs.push(format!("flashsize_{}", &chip_name[11..12]));
} else {
if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" {
cfgs.push("stm32h7rs".to_owned());
} else {
cfgs.push(chip_name[..7].to_owned()); // stm32f4
}
cfgs.push(chip_name[..9].to_owned()); // stm32f429
cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x
cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9
cfgs.push(format!("package_{}", &chip_name[9..10]));
cfgs.push(format!("flashsize_{}", &chip_name[10..11]));
}
// // Configs for targeting groups of chips
// if &chip_name[..8] == "stm32wba" {
// cfgs.push(chip_name[..8].to_owned()); // stm32wba
// cfgs.push(chip_name[..10].to_owned()); // stm32wba52
// cfgs.push(format!("package_{}", &chip_name[10..11]));
// cfgs.push(format!("flashsize_{}", &chip_name[11..12]));
// } else {
// if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" {
// cfgs.push("stm32h7rs".to_owned());
// } else {
// cfgs.push(chip_name[..7].to_owned()); // stm32f4
// }
// cfgs.push(chip_name[..9].to_owned()); // stm32f429
// cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x
// cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9
// cfgs.push(format!("package_{}", &chip_name[9..10]));
// cfgs.push(format!("flashsize_{}", &chip_name[10..11]));
// }

// Mark the L4+ chips as they have many differences to regular L4.
if &chip_name[..7] == "stm32l4" {
if "pqrs".contains(&chip_name[7..8]) {
cfgs.push("stm32l4_plus".to_owned());
} else {
cfgs.push("stm32l4_nonplus".to_owned());
}
}
// // Mark the L4+ chips as they have many differences to regular L4.
// if &chip_name[..7] == "stm32l4" {
// if "pqrs".contains(&chip_name[7..8]) {
// cfgs.push("stm32l4_plus".to_owned());
// } else {
// cfgs.push("stm32l4_nonplus".to_owned());
// }
// }

cfgs
}
// cfgs
// }

// cfgs.enable_all(&get_chip_cfgs(&chip_name));
// for &chip_name in ALL_CHIPS.iter() {
Expand Down
2 changes: 1 addition & 1 deletion examples/py32f030/src/bin/adc.rs
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Expand Up @@ -4,10 +4,10 @@

use defmt::*;
use embassy_executor::Spawner;
use embassy_time::Timer;
use py32_hal::adc::{Adc, SampleTime};
use py32_hal::peripherals::ADC;
use py32_hal::{adc, bind_interrupts};
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};

bind_interrupts!(struct Irqs {
Expand Down
2 changes: 1 addition & 1 deletion examples/py32f030/src/bin/blinky.rs
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Expand Up @@ -3,9 +3,9 @@
#![feature(impl_trait_in_assoc_type)]

use defmt::*;
use py32_hal::gpio::{Level, Output, Speed};
use embassy_executor::Spawner;
use embassy_time::Timer;
use py32_hal::gpio::{Level, Output, Speed};
use {defmt_rtt as _, panic_halt as _};

// main is itself an async function.
Expand Down
1 change: 0 additions & 1 deletion examples/py32f030/src/bin/button_exti.rs
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Expand Up @@ -28,4 +28,3 @@ async fn main(_spawner: Spawner) {
info!("Released!");
}
}

12 changes: 10 additions & 2 deletions examples/py32f030/src/bin/pwm.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@

use defmt::*;
use embassy_executor::Spawner;
use embassy_time::Timer;
use py32_hal::gpio::OutputType;
use py32_hal::time::khz;
use py32_hal::timer::simple_pwm::{PwmPin, SimplePwm};
use embassy_time::Timer;
use {defmt_rtt as _, panic_probe as _};

#[embassy_executor::main]
Expand All @@ -16,7 +16,15 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");

let ch4_pin = PwmPin::new_ch4(p.PA1, OutputType::PushPull);
let mut pwm = SimplePwm::new(p.TIM1, None, None, None, Some(ch4_pin), khz(10), Default::default());
let mut pwm = SimplePwm::new(
p.TIM1,
None,
None,
None,
Some(ch4_pin),
khz(10),
Default::default(),
);
let mut ch4 = pwm.ch4();
ch4.enable();

Expand Down
10 changes: 6 additions & 4 deletions examples/py32f030/src/bin/rcc_48mhz.rs
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@@ -1,18 +1,20 @@
#![no_std]
#![no_main]

use cortex_m_rt::entry;
use defmt::*;
use py32_hal::gpio::{Level, Output, Speed};
use py32_hal::rcc::{PllSource, Pll, Sysclk};
use py32_hal::rcc::{Pll, PllSource, Sysclk};
use py32_hal::time::Hertz;
use {defmt_rtt as _, panic_halt as _};
use cortex_m_rt::entry;

#[entry]
fn main() -> ! {
let mut cfg: py32_hal::Config = Default::default();
cfg.rcc.hsi = Some(Hertz::mhz(24));
cfg.rcc.pll = Some(Pll { src: PllSource::HSI });
cfg.rcc.pll = Some(Pll {
src: PllSource::HSI,
});
cfg.rcc.sys = Sysclk::PLL;
let p = py32_hal::init(cfg);

Expand All @@ -30,4 +32,4 @@ fn main() -> ! {

cortex_m::asm::delay(8_000_000);
}
}
}
8 changes: 4 additions & 4 deletions src/adc/v1.rs
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Expand Up @@ -176,10 +176,10 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
}

// pub fn set_ckmode(&mut self, ckmode: Ckmode) {
// // set ADC clock mode
// T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode));
// }
pub fn set_ckmode(&mut self, ckmode: Ckmode) {
// set ADC clock mode
T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode));
}

pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
let ch_num = channel.channel();
Expand Down
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