remove rawNuke (OpenXiangShan#2460)

Co-authored-by: Lyn <[email protected]>
pxk27 · Nov 6, 2023 · 59bf8b8 · 59bf8b8
1 parent d4d8c72
commit 59bf8b8
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Showing 5 changed files with 2 additions and 6 deletions.
diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
@@ -301,7 +301,6 @@ class MicroOpRbExt(implicit p: Parameters) extends XSBundleWithMicroOp {
 
 class Redirect(implicit p: Parameters) extends XSBundle {
   val isRVC = Bool()
-  val rawNuke = Bool()
   val robIdx = new RobPtr
   val ftqIdx = new FtqPtr
   val ftqOffset = UInt(log2Up(PredictWidth).W)

diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala
@@ -180,7 +180,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
   val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN)
   val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U)
   val target = Mux(s1_isReplay,
-    Mux(s1_redirect_bits_reg.rawNuke, real_pc, real_pc + Mux(s1_redirect_bits_reg.isRVC, 2.U, 4.U)),
+    Mux(s1_redirect_bits_reg.flushItself(), real_pc, real_pc + Mux(s1_redirect_bits_reg.isRVC, 2.U, 4.U)),
     Mux(s1_redirect_bits_reg.cfiUpdate.taken,
       Mux(s1_isJump, s1_jumpTarget, brTarget),
       snpc
@@ -209,7 +209,7 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
   val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset)
 
   // update load violation predictor if load violation redirect triggered
-  io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg && s2_redirect_bits_reg.rawNuke, init = false.B)
+  io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg && s2_redirect_bits_reg.flushItself(), init = false.B)
   // update wait table
   io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth))
   io.memPredUpdate.wdata := true.B

diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
@@ -376,7 +376,6 @@ class LoadQueueRAW(implicit p: Parameters) extends XSModule
   // check if rollback request is still valid in parallel
   io.rollback.bits             := DontCare
   io.rollback.bits.isRVC       := rollbackUop.cf.pd.isRVC
-  io.rollback.bits.rawNuke     := true.B
   io.rollback.bits.robIdx      := rollbackUop.robIdx
   io.rollback.bits.ftqIdx      := rollbackUop.cf.ftqPtr
   io.rollback.bits.stFtqIdx    := rollbackStFtqIdx

diff --git a/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
@@ -458,7 +458,6 @@ class UncacheBuffer(implicit p: Parameters) extends XSModule with HasCircularQue
 
   val (rollbackValid, rollbackUop) = detectRollback()
   io.rollback.bits           := DontCare
-  io.rollback.bits.rawNuke   := false.B
   io.rollback.bits.isRVC     := rollbackUop.cf.pd.isRVC
   io.rollback.bits.robIdx    := rollbackUop.robIdx
   io.rollback.bits.ftqIdx    := rollbackUop.cf.ftqPtr

diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
@@ -1071,7 +1071,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule
   io.rollback.valid := s3_out.valid && !s3_rep_frm_fetch && s3_flushPipe
   io.rollback.bits             := DontCare
   io.rollback.bits.isRVC       := s3_out.bits.uop.cf.pd.isRVC
-  io.rollback.bits.rawNuke     := false.B
   io.rollback.bits.robIdx      := s3_out.bits.uop.robIdx
   io.rollback.bits.ftqIdx      := s3_out.bits.uop.cf.ftqPtr
   io.rollback.bits.ftqOffset   := s3_out.bits.uop.cf.ftqOffset