Prepare for release:

- Clean up code
- Remove part related to address translation
- Add comments
- Fix some bugs
- Update RcUpdate command

Change-Id: I5a9ae0cd3945bf562b8608a8f01e3305da6c8aa5

configs/capstone/fast-forward.py

@@ -96,7 +96,7 @@ class L2Cache(Cache):
     tgts_per_mshr = 12
     # prefetcher = TaggedPrefetcher(degree=1, prefetch_on_access=True)
 
-system = System()
+system = System(mmap_using_noreserve=True)
 
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'

src/arch/riscvcapstone/RiscvMMU.py

@@ -49,13 +49,10 @@ class RiscvMMU(BaseMMU):
 
     itb = RiscvTLB(entry_type="instruction")
     dtb = RiscvTLB(entry_type="data")
-    pma_checker = Param.PMAChecker(PMAChecker(), "PMA Checker")
-    pmp = Param.PMP(PMP(), "Physical Memory Protection Unit")
 
     @classmethod
     def walkerPorts(cls):
-        return ["mmu.itb.walker.port", "mmu.dtb.walker.port"]
+        return []
 
     def connectWalkerPorts(self, iport, dport):
-        self.itb.walker.port = iport
-        self.dtb.walker.port = dport
+        pass

src/arch/riscvcapstone/RiscvTLB.py

@@ -43,9 +43,6 @@ class RiscvPagetableWalker(ClockedObject):
     system = Param.System(Parent.any, "system object")
     num_squash_per_cycle = Param.Unsigned(4,
             "Number of outstanding walks that can be squashed per cycle")
-    # Grab the pma_checker from the MMU
-    pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
-    pmp = Param.PMP(Parent.any, "PMP")
 
 class RiscvTLB(BaseTLB):
     type = 'RiscvTLB'
@@ -55,6 +52,3 @@ class RiscvTLB(BaseTLB):
     size = Param.Int(64, "TLB size")
     walker = Param.RiscvPagetableWalker(\
             RiscvPagetableWalker(), "page table walker")
-    # Grab the pma_checker from the MMU
-    pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
-    pmp  = Param.PMP(Parent.any, "Physical Memory Protection Unit")

src/arch/riscvcapstone/isa.cc

@@ -248,10 +248,6 @@ void ISA::clear()
     miscRegFile[MISCREG_TSELECT] = 1;
     // NMI is always enabled.
     miscRegFile[MISCREG_NMIE] = 1;
-
-    //probably need to set cinit here
-    //don't. do it in CPU instead
-    //else include hell awaits
 }
 
 bool
@@ -404,7 +400,6 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 void
 ISA::setMiscReg(int misc_reg, RegVal val)
 {
-    //maybe set this to update only when correct cwrld
     if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
         // Ignore writes to HPM counters for now
         warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
@@ -420,44 +415,12 @@ ISA::setMiscReg(int misc_reg, RegVal val)
           case MISCREG_PMPCFG0:
           case MISCREG_PMPCFG2:
             {
-                // PMP registers should only be modified in M mode
-                assert(readMiscRegNoEffect(MISCREG_PRV).intVal() == PRV_M);
-
-                // Specs do not seem to mention what should be
-                // configured first, cfg or address regs!
-                // qemu seems to update the tables when
-                // pmp addr regs are written (with the assumption
-                // that cfg regs are already written)
-
-                for (int i=0; i < sizeof(val); i++) {
-
-                    uint8_t cfg_val = (val >> (8*i)) & 0xff;
-                    auto mmu = dynamic_cast<RiscvcapstoneISA::MMU *>
-                                (tc->getMMUPtr());
-
-                    // Form pmp_index using the index i and
-                    // PMPCFG register number
-                    // Note: MISCREG_PMPCFG2 - MISCREG_PMPCFG0 = 1
-                    // 8*(misc_reg-MISCREG_PMPCFG0) will be useful
-                    // if a system contains more than 16 PMP entries
-                    uint32_t pmp_index = i+(8*(misc_reg-MISCREG_PMPCFG0));
-                    mmu->getPMP()->pmpUpdateCfg(pmp_index,cfg_val);
-                }
-
-                setMiscRegNoEffect(misc_reg, val);
+                panic("pmp unsupported.");
             }
             break;
           case MISCREG_PMPADDR00 ... MISCREG_PMPADDR15:
             {
-                // PMP registers should only be modified in M mode
-                assert(readMiscRegNoEffect(MISCREG_PRV).intVal() == PRV_M);
-
-                auto mmu = dynamic_cast<RiscvcapstoneISA::MMU *>
-                              (tc->getMMUPtr());
-                uint32_t pmp_index = misc_reg-MISCREG_PMPADDR00;
-                mmu->getPMP()->pmpUpdateAddr(pmp_index, val);
-
-                setMiscRegNoEffect(misc_reg, val);
+                panic("pmp unsupported.");
             }
             break;