Cherrypick c7600d3: Re-issue rescheduled load

Change-Id: I2dbe0754f0e7a5283a45080f461ff050831bd1b1
project-starch · Sep 8, 2023 · ac49345 · ac49345
2 parents b179428 + c7600d3
commit ac49345
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Showing 6 changed files with 14 additions and 8 deletions.
diff --git a/src/arch/riscvcapstone/isa/formats/tags.isa b/src/arch/riscvcapstone/isa/formats/tags.isa
@@ -110,6 +110,8 @@ def template TagAccessExecute {{
 
         %(code)s;
 
+        dyn_inst->setLoadEffAddrs(EA, 1);
+
         return NoFault;
     }
 }};

diff --git a/src/arch/riscvcapstone/o3/commit.cc b/src/arch/riscvcapstone/o3/commit.cc
@@ -1228,7 +1228,7 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
     //seriously, there has to be a better way to do this.
     //how would split change RC? need to check the spec
     std::string mnemonic = head_inst->staticInst->getName();
-    if(head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" &&
+    if(head_inst->fault != NoFault && head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" &&
         mnemonic != "captype" && mnemonic != "capnode" &&
         mnemonic != "capbound" && mnemonic != "stc" &&
         mnemonic != "std" && mnemonic != "stb" &&

diff --git a/src/arch/riscvcapstone/o3/iew.cc b/src/arch/riscvcapstone/o3/iew.cc
@@ -1295,7 +1295,10 @@ IEW::executeInsts()
         if(fault == NoFault) {
             DPRINTF(IEW, "Execute instruction %i -> %s\n", inst->seqNum, inst->staticInst->getName());
             fault = inst->execute();
-            inst->setExecuteCalled();
+            //only one case will not mark executecalled -> when it's a rescheduled load
+            if(!inst->isLoad() || (inst->isLoad() && inst->loadEffAddrValid()) || inst->fault != NoFault)
+                inst->setExecuteCalled();
+
             if(inst->isMemRef()) {
                 DPRINTF(IEW, "Memref fault = %d\n", fault == NoFault);
             } else {

diff --git a/src/arch/riscvcapstone/o3/inst_queue.cc b/src/arch/riscvcapstone/o3/inst_queue.cc
@@ -1097,7 +1097,6 @@ InstructionQueue::rescheduleMemInst(const DynInstPtr &resched_inst)
     resched_inst->translationCompleted(false);
 
     resched_inst->clearCanIssue();
-    //resched_inst->clearExecuteCalled();
     memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
 }
 

diff --git a/src/arch/riscvcapstone/o3/lsq_unit.cc b/src/arch/riscvcapstone/o3/lsq_unit.cc
@@ -473,7 +473,7 @@ LSQUnit::checkSnoop(PacketPtr pkt)
     LSQRequest *request = iter->request();
 
     // Check that this snoop didn't just invalidate our lock flag
-    if (ld_inst->effAddrValid() &&
+    if (ld_inst->loadEffAddrValid() &&
         request->isCacheBlockHit(invalidate_addr, cacheBlockMask)
         && ld_inst->memReqFlags & Request::LLSC) {
         ld_inst->tcBase()->getIsaPtr()->handleLockedSnoopHit(ld_inst.get());
@@ -485,7 +485,7 @@ LSQUnit::checkSnoop(PacketPtr pkt)
         ld_inst = iter->instruction();
         assert(ld_inst);
         request = iter->request();
-        if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered())
+        if (!ld_inst->loadEffAddrValid() || ld_inst->strictlyOrdered())
             continue;
 
         DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n",
@@ -1435,7 +1435,7 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx)
         // rescheduled eventually
         iewStage->rescheduleMemInst(load_inst);
         load_inst->clearIssued();
-        load_inst->effAddrValid(false);
+        load_inst->loadEffAddrValid(false);
         ++stats.rescheduledLoads;
         DPRINTF(LSQUnit, "Strictly ordered load [sn:%lli] PC %s\n",
                 load_inst->seqNum, load_inst->pcState());
@@ -1659,7 +1659,8 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx)
                 // rescheduled eventually
                 iewStage->rescheduleMemInst(load_inst);
                 load_inst->clearIssued();
-                load_inst->effAddrValid(false);
+                load_inst->loadEffAddrValid(false);
+                load_inst->memReadN--; //maybe we need to change it to 0: insns with multiple loads
                 ++stats.rescheduledLoads;
 
                 // Do not generate a writeback event as this instruction is not

diff --git a/src/arch/riscvcapstone/o3/ncq_unit.cc b/src/arch/riscvcapstone/o3/ncq_unit.cc
@@ -92,7 +92,8 @@ NCQUnit::cleanupCommands(){
     DPRINTF(NCQ, "Cleaning up commands\n");
     while(!ncQueue.empty()) {
         auto& front = ncQueue.front();
-        DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completed() %u, commands size() %u", front.inst->seqNum, front.canWB, front.completed(), front.commands.size());
+        DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completedCommands %u, commands size() %u\n",
+                front.inst->seqNum, front.canWB, front.completedCommands, front.commands.size());
         if(front.canWB && front.completed()) {
             DPRINTF(NCQ, "Removing NCQEntry for instruction %u\n", front.inst->seqNum);
             front.inst->ncqIdx = -1;