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RC update optimization (WIP):
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    - Commit stage currently updates refcount of the prev dest phys reg of an inst

Change-Id: I142a91e25bd4590df75d7c72bf651ec41d23285f
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@hakase56557
hakase56557 committed Jul 19, 2023
1 parent 790d74e commit 5dece40
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Showing 19 changed files with 272 additions and 116 deletions.
110 changes: 54 additions & 56 deletions src/arch/riscvcapstone/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -564,7 +564,6 @@ decode QUADRANT default Unknown::unknown() {
format RNodeOp {
0xc: movc ({{
//Rd holds a cap
//TODO: check tag bit
//RcUpdate-1 for Rd if it holds a capability
//Check Rs, if it's non-linear cap, RcUpdate+1
//otherwise do nothing
Expand All @@ -574,12 +573,12 @@ decode QUADRANT default Unknown::unknown() {
DynInst* dyn_inst = dynamic_cast<DynInst*>(xc);
assert(dyn_inst);

const RegVal& rdv = Rd_trv.getRegVal();
/*const RegVal& rdv = Rd_trv.getRegVal();
if(Rd_trv.getTag()) {
uint64_t node_id = rdv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(node_id, -1));
}
}*/

Rd_trv = Rs1_trv;

Expand Down Expand Up @@ -634,8 +633,8 @@ decode QUADRANT default Unknown::unknown() {
0xe: ldc ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
//@todo: if Rd already holds a capability, need to reduce the refcount
//now being handled by rename stage
Expand All @@ -645,9 +644,9 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Illegal read - out of capability bounds!", machInst);

//Fault fault = dyn_inst->initiateGetTag(EA);
//if(fault != NoFault)
// return fault;
Fault fault = dyn_inst->initiateGetTag(EA);
if(fault != NoFault)
return fault;

//DPRINTFN("MemReads count = %d, tag query count = %d\n",
// dyn_inst->memReadN, dyn_inst->tagQueryN);
Expand All @@ -662,6 +661,9 @@ decode QUADRANT default Unknown::unknown() {
return std::make_shared<IllegalInstFault>(
"Rs1 doesn't have the necessary perms", machInst);
}}, {{
bool tag_res = dyn_inst->getTagQueryRes(0);
assert(tag_res);

ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();

Expand All @@ -674,29 +676,25 @@ decode QUADRANT default Unknown::unknown() {

Addr EA = Rs1_trv.getRegVal().capVal().cursor();

//bool tag_res = dyn_inst->getTagQueryRes(0);
//assert(tag_res);

//if load result is a linear type
// clear tag bit from EA
// clear the mem location itself
//otherwise do RcUpdate+1 on the node

/*if(Rd_trv.getRegVal().capVal().type() != CapType::NONLIN) {
if(Mem_rv.capVal().type() != CapType::NONLIN) {
dyn_inst->initiateSetTag(EA, false);
} else {
NodeID node_id = Rd_trv.getRegVal().capVal().nodeId();
NodeID node_id = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(node_id, 1));
}*/
}

Rd_trv = temp_regval;
//Rd_trv.setTag(true);
}});
0x13: lds ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

Expand Down Expand Up @@ -729,16 +727,16 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.setTag(false);

//in execute or completeAcc hmmm
//Addr EA = Rs1_trv.getRegVal().capVal().cursor();
//dyn_inst->initiateSetTag(EA, false);
Addr EA = Rs1_trv.getRegVal().capVal().cursor();
dyn_inst->initiateSetTag(EA, false);

Rd_trv = temp_regval;
}});
0x16: ldb ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

Expand All @@ -760,7 +758,7 @@ decode QUADRANT default Unknown::unknown() {
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
//Fault fault = dyn_inst->initiateGetTag(EA);
Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
Expand All @@ -773,21 +771,21 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.getRegVal() = (uint8_t)Mem_rv;
temp_regval.setTag(false);

//bool tag_res = dyn_inst->getTagQueryRes(0);
//if(tag_res) {
// dyn_inst->initiateSetTag(EA, false);
// NodeID nodeId = Mem_rv.capVal().nodeId();
// dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
//}
bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
}});
0x17: ldd ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

Expand All @@ -809,7 +807,7 @@ decode QUADRANT default Unknown::unknown() {
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
//Fault fault = dyn_inst->initiateGetTag(EA);
Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
Expand All @@ -822,21 +820,21 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.getRegVal() = (uint64_t)Mem_rv;
temp_regval.setTag(false);

//bool tag_res = dyn_inst->getTagQueryRes(0);
//if(tag_res) {
// dyn_inst->initiateSetTag(EA, false);
// NodeID nodeId = Mem_rv.capVal().nodeId();
// dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
//}
bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
}});
0x18: ldh ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

Expand All @@ -858,7 +856,7 @@ decode QUADRANT default Unknown::unknown() {
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
//Fault fault = dyn_inst->initiateGetTag(EA);
Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
Expand All @@ -871,21 +869,21 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.getRegVal() = (uint16_t)Mem_rv;
temp_regval.setTag(false);

//bool tag_res = dyn_inst->getTagQueryRes(0);
//if(tag_res) {
// dyn_inst->initiateSetTag(EA, false);
// NodeID nodeId = Mem_rv.capVal().nodeId();
// dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
//}
bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
}});
0x19: ldw ({{
assert(Rs1_trv.getTag());

//NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
//dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeQuery(node_id));
}}, {{
Addr EA = Rs1_trv.getRegVal().capVal().cursor();

Expand All @@ -907,7 +905,7 @@ decode QUADRANT default Unknown::unknown() {
"Rs1 doesn't have the necessary perms", machInst);

EA = EA & ~(sizeof(RegVal) - 1);
//Fault fault = dyn_inst->initiateGetTag(EA);
Fault fault = dyn_inst->initiateGetTag(EA);
}}, {{
ConstTaggedRegVal temp_regval;
gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal();
Expand All @@ -920,12 +918,12 @@ decode QUADRANT default Unknown::unknown() {
temp_regval.getRegVal() = (uint32_t)Mem_rv;
temp_regval.setTag(false);

//bool tag_res = dyn_inst->getTagQueryRes(0);
//if(tag_res) {
// dyn_inst->initiateSetTag(EA, false);
// NodeID nodeId = Mem_rv.capVal().nodeId();
// dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
//}
bool tag_res = dyn_inst->getTagQueryRes(0);
if(tag_res) {
dyn_inst->initiateSetTag(EA, false);
NodeID nodeId = Mem_rv.capVal().nodeId();
dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1));
}

Rd_trv = temp_regval;
//Rd_trv.setTag(false);
Expand Down Expand Up @@ -1371,7 +1369,7 @@ decode QUADRANT default Unknown::unknown() {
DynInst* dyn_inst = dynamic_cast<DynInst*>(xc);
assert(dyn_inst);

NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId();
NodeID node_id = Rs1_ud;
dyn_inst->initiateNodeCommand(new NodeQueryDbg(node_id));
}}, IsSerializing, IsNonSpeculative);
}
Expand Down
2 changes: 1 addition & 1 deletion src/arch/riscvcapstone/isa/formats/rnode.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ def template RNodeMemConstructor {{
%(set_reg_idx_arr)s;
%(constructor)s;

//hasNodeOp = true;
hasNodeOp = true;
}
}};

Expand Down
33 changes: 33 additions & 0 deletions src/arch/riscvcapstone/o3/commit.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1212,6 +1212,39 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
}
}

DPRINTF(Commit, "Issuing node commands for inst PC %s [sn:%u]\n", head_inst->pcState(), head_inst->seqNum);
// for (unsigned i = 0; i < nodeFromRename->size; i++) {
// DPRINTF(Commit, "NodeID: %u\n", nodeFromRename->cmds[i].first);
// if(nodeFromRename->insts[i]->seqNum == head_inst->seqNum) {
// NodeID node_id = nodeFromRename->cmds[i].first;
// int delta = nodeFromRename->cmds[i].second;

// DPRINTF(Commit, "Doing RcUpdate for NodeID: %u, delta: %d\n", node_id, delta);

// head_inst->initiateNodeCommand(new NodeRcUpdate(node_id, delta));
// }
// }
//very, very hacked together
if(head_inst->staticInst->opClass() != No_OpClass && head_inst->staticInst->getName() != "captype"
&& head_inst->staticInst->getName() != "capperm" && head_inst->staticInst->getName() != "capnode") {
CPU* cpu = dynamic_cast<o3::CPU *>(head_inst->getCpuPtr());
PhysRegIdPtr prev_reg = head_inst->prevDestIdx(0);
if(!(prev_reg->classValue() == InvalidRegClass || prev_reg->classValue() == MiscRegClass)) {
TaggedRegVal tagged_reg = cpu->getWritableTaggedReg(prev_reg);
if(tagged_reg.getTag()) {
tagged_reg.setTag(false);
NodeID node_id = tagged_reg.getRegVal().capVal().nodeId();
NodeCommandPtr cmd;
// cmd = new NodeRcUpdate(node_id, -1);
// cmd->setCPU(cpu);
// cmd->setSeqNum(head_inst->seqNum);
cpu->pushNodeCommand(new NodeRcUpdate(cpu, head_inst->seqNum, node_id, -1));
cpu->setTaggedReg(prev_reg, tagged_reg);
DPRINTF(Commit, "Issued RcUpdate for nodeId = %u\n", node_id);
}
}
}

// hardware transactional memory
// if a fault occurred within a HTM transaction
// ensure that the transaction aborts
Expand Down
4 changes: 4 additions & 0 deletions src/arch/riscvcapstone/o3/cpu.hh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -671,6 +671,10 @@ class CPU : public BaseCPU
return iew.ncQueue.pushCommand(inst, cmd);
}

Fault pushNodeCommand(NodeCommandPtr cmd) {
return iew.ncQueue.pushCommand(cmd);
}

QueryResult passedQuery(const DynInstPtr& inst) const {
return iew.ncQueue.passedQuery(inst);
}
Expand Down
6 changes: 6 additions & 0 deletions src/arch/riscvcapstone/o3/ncq.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,12 @@ NCQ::pushCommand(const DynInstPtr& inst, NodeCommandPtr cmd) {
return threads[inst->threadNumber].pushCommand(inst, cmd);
}

Fault
NCQ::pushCommand(NodeCommandPtr cmd) {
DPRINTF(NCQ, "Commit: Push command to NCQ\n");
return threads[0].pushCommand(cmd);
}

bool
NCQ::isFull(ThreadID thread_id) {
assert(thread_id >= 0 && thread_id < threadNum);
Expand Down
1 change: 1 addition & 0 deletions src/arch/riscvcapstone/o3/ncq.hh
View file
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,7 @@ class NCQ {
bool isFull(ThreadID thread_id);

Fault pushCommand(const DynInstPtr& inst, NodeCommandPtr cmd);
Fault pushCommand(NodeCommandPtr cmd);

void commitBefore(InstSeqNum seq_num, ThreadID thread_id);
void writebackCommands();
Expand Down
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