ultrascale: geometry extractor support for csec, hdiolc.

prjcombine_rawdump/src/bin/rd2html.rs

@@ -1806,6 +1806,9 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("INT_INTF_LEFT_IBRK_PCIE4_TERM_H_FT", SINGLE, &[]),
     TileInfo("INT_INTF_R_PCIE4", SINGLE, &["int-if"]),
     TileInfo("INT_INTF_RIGHT_TERM_HDIO_FT", SINGLE, &["int-if"]),
+    TileInfo("INT_INTF_RIGHT_TERM_HDIO_RBRK_FT", SINGLE, &["clk-brk"]),
+    TileInfo("INT_INTF_RIGHT_TERM_HDIO_TERM_B_FT", SINGLE, &[]),
+    TileInfo("INT_INTF_RIGHT_TERM_HDIO_TERM_T_FT", SINGLE, &[]),
     TileInfo("RCLK_INTF_R_IBRK_L", SINGLE, &["clk-row"]),
     TileInfo("RCLK_RCLK_INTF_RIGHT_IBRK_PCIE4_R_FT", SINGLE, &["clk-row"]),
     TileInfo("INT_INTF_R_PCIE4_RBRK", SINGLE, &["clk-brk"]),
@@ -1815,6 +1818,7 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("INT_INTF_RIGHT_IBRK_PCIE4_TERM_H_FT", SINGLE, &[]),
     TileInfo("INT_INTF_LEFT_TERM_IO_FT", SINGLE, &["int-if"]),
     TileInfo("RCLK_RCLK_INTF_LEFT_TERM_IO_FT", SINGLE, &["clk-row"]),
+    TileInfo("RCLK_RCLK_INTF_LEFT_TERM_IO_DL3_FT", SINGLE, &["clk-row"]),
     TileInfo("INT_INTF_LEFT_TERM_IO_RBRK_FT", SINGLE, &["clk-brk"]),
     TileInfo("INT_INTF_LEFT_TERM_IO_TERM_B_FT", SINGLE, &[]),
     TileInfo("INT_INTF_LEFT_TERM_IO_TERM_T_FT", SINGLE, &[]),
@@ -1908,6 +1912,7 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     // left
     TileInfo("BRAM", (0, 0, 4, 0), &["bram"]),
     TileInfo("RCLK_BRAM_INTF_L", (1, 0, 0, 0), &["clk-row-buf"]), // quad bufs
+    TileInfo("RCLK_BRAM_INTF_R", (1, 0, 0, 0), &["clk-row-buf"]), // quad bufs
     TileInfo("RCLK_BRAM_INTF_TD_L", (1, 0, 0, 0), &["clk-row-buf"]), // quad bufs
     TileInfo("RCLK_BRAM_INTF_TD_R", (1, 0, 0, 0), &["clk-row-buf"]), // quad bufs
     TileInfo("BRAM_RBRK", SINGLE, &["clk-brk"]),
@@ -1967,10 +1972,13 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("HDIO_HDIO_RIGHT_TERM_P_FT", (1, 0, 0, 0), &[]),
     TileInfo("HDIO_HDIO_FILL_TERM_T_FT", SINGLE, &[]),
     TileInfo("CFG_CONFIG", (1, 0, 60, 0), &["cfg"]),
+    TileInfo("CSEC_CONFIG_FT", (2, 0, 60, 0), &["cfg"]),
     TileInfo("CFGIO_IOB20", (1, 0, 29, 0), &["cfg"]),
+    TileInfo("CFGIOLC_IOB20_FT", (1, 0, 29, 0), &["cfg"]),
     TileInfo("AMS", (1, 0, 29, 0), &["sysmon"]),
     TileInfo("RCLK_AMS_CFGIO", (1, 0, 0, 0), &["clk-row"]),
     TileInfo("CFGIO_CONFIG_RBRK", (1, 0, 0, 0), &["clk-brk"]),
+    TileInfo("CFGIOLC_CONFIG_SEC_RBRK_FT", (2, 0, 0, 0), &["clk-brk"]),
     TileInfo("CFG_CONFIG_PCIE4", (1, 0, 0, 0), &["clk-brk"]),
     TileInfo("AMS_TERM_T", (1, 0, 0, 0), &[]),
     TileInfo("CMAC_AMS_RBRK_FT", (1, 0, 0, 0), &["clk-brk"]),
@@ -1990,8 +1998,11 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("CFG_CFG_FILL_OLY_FT", (0, 0, 60, 0), &[]),
     TileInfo("CFG_CFG_FILL_OLY_DK_FT", (0, 0, 60, 0), &[]),
     TileInfo("CFGIO_FILL_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFGIO_FILL_LC_FT", (0, 0, 29, 0), &[]),
     TileInfo("AMS_AMS_FILL_FT", (0, 0, 29, 0), &[]),
+    TileInfo("AMS_AMS_FILL_LC_FT", (0, 0, 29, 0), &[]),
     TileInfo("RCLK_RCLK_CTR_FILL_FT", SINGLE, &["clk-row"]),
+    TileInfo("RCLK_RCLK_CTR_FILL_LC_FT", SINGLE, &["clk-row"]),
     TileInfo("CFGIO_CFG_FILL_RBRK_FT", SINGLE, &["clk-brk"]),
     TileInfo("CFG_CFG_FILL_RBRK_FT", SINGLE, &["clk-brk"]),
     TileInfo("CFG_CFG_CMAC_FILL_RBRK_FT", SINGLE, &["clk-brk"]),
@@ -2027,6 +2038,7 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("PCIE4_TERM_H_FT", (2, 0, 0, 0), &[]),
     TileInfo("CMAC_TERM_B", (2, 0, 0, 0), &[]),
     TileInfo("DFE_DFE_TILEG_TERM_B_FT", (2, 0, 0, 0), &[]),
+    TileInfo("CSEC_CONFIG_TERM_B_FT", (2, 0, 0, 0), &[]),
     TileInfo("CMAC_CMAC_TERM_T_FT", (2, 0, 0, 0), &[]),
     TileInfo("CMAC_CMAC_TERM_P_FT", (2, 0, 0, 0), &[]),
     TileInfo("CMAC_CMAC_CFG_TERM_T_FT", (2, 0, 0, 0), &[]),
@@ -2093,6 +2105,7 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     // HPIO left [outer]: HPIO_TERM, IBRK_FSR2IO, IOB, special CBRK, IBRK, XIPHY, CMT, INT_LEFT_IO
     // HPIO left [inner]: ..., IOB, special CBRK, ..., XIPHY, CMT, INT_CMT_L
     TileInfo("HPIO_TERM_L_FT", (1, 0, 29, 0), &[]),
+    TileInfo("HPIO_LASSEN_AMS_TERM_L_FT", (1, 0, 29, 0), &[]),
     TileInfo("HPIO_AUX_IO_TERM_L_BOT_FT", (1, 0, 29, 0), &[]),
     TileInfo("HPIO_AUX_IO_TERM_L_TOP_FT", (1, 0, 29, 0), &[]),
     TileInfo("HPIO_CFG_TERM_L_BOT_FT", (1, 0, 29, 0), &[]),
@@ -2236,6 +2249,32 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     ),
     TileInfo("RFADC_RFADC_RIGHT_TERM_B_FT", (50, 0, 0, 0), &[]),
     TileInfo("RFDAC_RFDAC_RIGHT_TERM_T_FT", (50, 0, 0, 0), &[]),
+    // right extra-large HDIO
+    TileInfo("HDIOLC_HDIOL_BOT_RIGHT_CFG_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("HDIOLC_HDIOL_TOP_RIGHT_CFG_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("HDIOLC_HDIOL_BOT_RIGHT_AUX_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("HDIOLC_HDIOL_TOP_RIGHT_AUX_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("RCLK_RCLK_HDIOL_R_FT", (44, 0, 0, 0), &["clk-row"]),
+    TileInfo(
+        "HDIOLC_HDIOL_RIGHT_TERM_RBRK_FT",
+        (44, 0, 0, 0),
+        &["clk-brk"],
+    ),
+    TileInfo("HDIOLC_HDIOL_RIGHT_TERM_B_FT", (44, 0, 0, 0), &[]),
+    TileInfo("HDIOLC_HDIOL_RIGHT_TERM_T_FT", (44, 0, 0, 0), &[]),
+    // left extra-large HDIO
+    TileInfo("HDIOLC_HDIOL_BOT_LEFT_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("HDIOLC_HDIOL_TOP_LEFT_FT", (44, 0, 29, 0), &["io"]),
+    TileInfo("RCLK_RCLK_HDIOL_L_FT", (44, 0, 0, 0), &["clk-row"]),
+    TileInfo("HDIOLC_HDIOL_LEFT_TERM_B_FT", (44, 0, 0, 0), &[]),
+    TileInfo("XIPHY_XIPHY_TERM_LEFT_FT", (0, 0, 14, 0), &[]),
+    TileInfo("RCLK_RCLK_XIPHY_TERM_L_FT", SINGLE, &["clk-row"]),
+    TileInfo("XIPHY_XIPHY_TERM_LEFT_RBRK_FT", SINGLE, &["clk-brk"]),
+    TileInfo("XIPHY_XIPHY_TERM_LEFT_TERM_B_FT", SINGLE, &[]),
+    TileInfo("CMT_CMT_LEFT_DL3_FT", (0, 0, 60, 0), &["pll"]),
+    TileInfo("HPIO_HDIOL_FILL_FT", (1, 0, 60, 0), &[]),
+    TileInfo("HPIO_HDIOL_FILL_TERM_B_FT", (1, 0, 0, 0), &[]),
+    TileInfo("HPIO_HDIOL_LEFT_RBRK_FT", (48, 0, 0, 0), &["clk-brk"]),
     // left
     TileInfo("GTH_QUAD_LEFT", (50, 0, 60, 0), &["gth"]),
     TileInfo("GTH_QUAD_LEFT_RBRK", (50, 0, 0, 0), &["clk-brk"]),
@@ -2329,6 +2368,8 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     ),
     TileInfo("AMS_M12BUF_SYSMON_BOT_L_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("AMS_M12BUF_SYSMON_TOP_L_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_TERM_BOT_L_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_TERM_TOP_L_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("CFG_M12BUF", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_TERM_L", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CFG_BOT_L_FT", (0, 0, 29, 0), &[]),
@@ -2349,6 +2390,8 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
         (0, 0, 29, 0),
         &[],
     ),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_TERM_BOT_L_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_TERM_TOP_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_RBRK_L", SINGLE, &["clk-brk"]),
     TileInfo("CFG_M12BUF_TERM_B_L", SINGLE, &[]),
     TileInfo("CFG_M12BUF_TERM_P", SINGLE, &[]),
@@ -2378,13 +2421,23 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("CFG_M12BUF_IO_CFG_ALTO_OLY_DK_TOP_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_IO_CFG_ALTO_BOT_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_IO_CFG_ALTO_TOP_L_FT", (0, 0, 29, 0), &[]),
+    // specials for left HDIOLC
+    TileInfo("CFRM_CBRK_HDIOL_L_FT", (0, 0, 29, 0), &["vbrk"]),
+    TileInfo("RCLK_RCLK_CBRK_HDIOL_M12BUF_L_FT", (1, 0, 0, 0), &["clk-row"]),
+    TileInfo("CFG_M12BUF_HDIOL_L_FT", (0, 0, 29, 0), &[]),
     // specials for left of cfg col
     TileInfo("CFRM_CBRK_CTR_RIGHT_L_FT", (0, 0, 29, 0), &["vbrk"]),
+    TileInfo("CFRM_CBRK_CTR_RIGHT_R_FT", (0, 0, 29, 0), &["vbrk"]),
     TileInfo(
         "RCLK_RCLK_CBRK_CTR_RIGHT_M12BUF_L_FT",
         (1, 0, 0, 0),
         &["clk-row"],
     ),
+    TileInfo(
+        "RCLK_RCLK_CBRK_CTR_RIGHT_M12BUF_R_FT",
+        (1, 0, 0, 0),
+        &["clk-row"],
+    ),
     TileInfo(
         "AMS_M12BUF_CTR_RIGHT_AMS_ALTO_BOT_L_FT",
         (0, 0, 29, 0),
@@ -2397,11 +2450,17 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     ),
     TileInfo("AMS_M12BUF_CTR_RIGHT_BOT_L_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("AMS_M12BUF_CTR_RIGHT_TOP_L_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_CTR_RIGHT_BOT_R_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_CTR_RIGHT_TOP_R_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_IO_BOT_L_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_IO_TOP_L_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("CFG_M12BUF_CTR_RIGHT_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CTR_RIGHT_CFG_OLY_BOT_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CTR_RIGHT_CFG_OLY_TOP_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CTR_RIGHT_CFG_ALTO_BOT_L_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CTR_RIGHT_CFG_ALTO_TOP_L_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_IO_BOT_L_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_IO_TOP_L_FT", (0, 0, 29, 0), &[]),
     TileInfo(
         "CFG_M12BUF_CTR_RIGHT_CFG_ALTO_TERM_TOP_L_FT",
         (0, 0, 29, 0),
@@ -2422,6 +2481,8 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
         (0, 0, 29, 0),
         &[],
     ),
+    TileInfo("CFG_M12BUF_CTR_RIGHT_BOT_R_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CTR_RIGHT_TOP_R_FT", (0, 0, 29, 0), &[]),
     // specials for right of hardip col
     TileInfo("CFRM_CBRK_CTR_LEFT_L_FT", (0, 0, 29, 0), &["vbrk"]),
     TileInfo(
@@ -2463,10 +2524,14 @@ const ULTRASCALEPLUS_TILES: &[TileInfo] = &[
     TileInfo("AMS_M12BUF_TOP_R_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("AMS_M12BUF_AMS_BOT_R_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("AMS_M12BUF_AMS_TOP_R_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_IO_BOT_R_FT", (0, 0, 29, 0), &["sysmon"]),
+    TileInfo("AMS_M12BUF_AMS_LASSEN_IO_TOP_R_FT", (0, 0, 29, 0), &["sysmon"]),
     TileInfo("CFG_M12BUF_CFG_BOT_R", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CFG_TOP_R", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CFG_BOT_R_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_CFG_TOP_R_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_IO_BOT_R_FT", (0, 0, 29, 0), &[]),
+    TileInfo("CFG_M12BUF_CFG_LASSEN_IO_TOP_R_FT", (0, 0, 29, 0), &[]),
     TileInfo("CFG_M12BUF_RBRK_R", SINGLE, &["clk-brk"]),
     TileInfo("CFG_M12BUF_TERM_B_R", SINGLE, &[]),
     TileInfo("CFG_M12BUF_TERM_T_R", SINGLE, &[]),

prjcombine_rdbuild/src/lib.rs

@@ -92,6 +92,7 @@ impl PartBuilder {
 
     fn slotify<'a>(
         &mut self,
+        tile_kind: &str,
         sites: &'a [(&'a str, &'a str, Vec<PbSitePin<'a>>)],
     ) -> HashMap<&'a str, TkSiteSlot> {
         fn from_pinnum(pins: &[PbSitePin<'_>], refpin: &str) -> u8 {
@@ -260,9 +261,18 @@ impl PartBuilder {
                 };
                 TkSiteSlot::Indexed(self.part.slot_kinds.get_or_insert(k), idx)
             } else if let Some((base, x, y)) = split_xy(n) {
-                let base = self.part.slot_kinds.get_or_insert(base);
-                let (bx, by) = minxy[&base];
-                TkSiteSlot::Xy(base, (x - bx) as u8, (y - by) as u8)
+                let base_id = self.part.slot_kinds.get_or_insert(base);
+                let (bx, by) = minxy[&base_id];
+                let x = x - bx;
+                let mut y = y - by;
+                if self.part.family == "ultrascaleplus"
+                    && tile_kind == "HPIO_L"
+                    && base == "IOB"
+                    && y >= 30
+                {
+                    y -= 17;
+                }
+                TkSiteSlot::Xy(base_id, x as u8, y as u8)
             } else if let Some((base, _s, x, y)) = split_sxy(n) {
                 let base = self.part.slot_kinds.get_or_insert(base);
                 let (bx, by) = minxy[&base];
@@ -399,7 +409,7 @@ impl PartBuilder {
                 )
             })
             .collect();
-        let slots = self.slotify(sites);
+        let slots = self.slotify(&kind, sites);
         let sites_raw: Vec<_> = sites
             .iter()
             .map(|&(n, k, ref p)| {

prjcombine_ultrascale/src/bond.rs

@@ -1,10 +1,8 @@
-use prjcombine_int::grid::DieId;
+use prjcombine_int::grid::{DieId, TileIobId};
 use serde::{Deserialize, Serialize};
 use serde_json::json;
 use std::collections::BTreeMap;
 
-use crate::grid::{HdioIobId, HpioIobId};
-
 #[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd, Hash, Serialize, Deserialize)]
 pub enum CfgPin {
     Tck,
@@ -144,8 +142,9 @@ pub enum RfAdcPin {
 #[derive(Copy, Clone, Debug, Eq, PartialEq, Ord, PartialOrd, Hash, Serialize, Deserialize)]
 pub enum BondPin {
     // bank, bel idx
-    Hpio(u32, HpioIobId),
-    Hdio(u32, HdioIobId),
+    Hpio(u32, TileIobId),
+    Hdio(u32, TileIobId),
+    HdioLc(u32, TileIobId),
     IoVref(u32),
     // bank, type
     Gt(u32, GtPin),
@@ -225,13 +224,20 @@ pub enum SharedCfgPin {
     SmbAlert, // Ultrascale+ only
     PerstN0,
     PerstN1, // Ultrascale only (shared with I2C_SDA on Ultrascale+)
+    // CSEC new stuff
+    Busy,
+    Fcs1B,
+    OspiDs,
+    OspiRstB,
+    OspiEccFail,
 }
 
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub struct ExpandedBond<'a> {
     pub bond: &'a Bond,
-    pub hpios: BTreeMap<(u32, HpioIobId), String>,
-    pub hdios: BTreeMap<(u32, HdioIobId), String>,
+    pub hpios: BTreeMap<(u32, TileIobId), String>,
+    pub hdios: BTreeMap<(u32, TileIobId), String>,
+    pub hdiolcs: BTreeMap<(u32, TileIobId), String>,
     pub gts: BTreeMap<(u32, GtPin), String>,
     pub sysmons: BTreeMap<(DieId, SysMonPin), String>,
 }
@@ -240,6 +246,7 @@ impl Bond {
     pub fn expand(&self) -> ExpandedBond {
         let mut hpios = BTreeMap::new();
         let mut hdios = BTreeMap::new();
+        let mut hdiolcs = BTreeMap::new();
         let mut gts = BTreeMap::new();
         let mut sysmons = BTreeMap::new();
         for (name, pad) in &self.pins {
@@ -250,6 +257,9 @@ impl Bond {
                 BondPin::Hdio(bank, idx) => {
                     hdios.insert((bank, idx), name.clone());
                 }
+                BondPin::HdioLc(bank, idx) => {
+                    hdiolcs.insert((bank, idx), name.clone());
+                }
                 BondPin::Gt(bank, gtpin) => {
                     gts.insert((bank, gtpin), name.clone());
                 }
@@ -263,6 +273,7 @@ impl Bond {
             bond: self,
             hpios,
             hdios,
+            hdiolcs,
             gts,
             sysmons,
         }
@@ -274,6 +285,7 @@ impl Bond {
                 self.pins.iter().map(|(pin, pad)| (pin.clone(), match pad {
                     BondPin::Hpio(bank, io) => format!("HPIO:{bank}:{io}"),
                     BondPin::Hdio(bank, io) => format!("HDIO:{bank}:{io}"),
+                    BondPin::HdioLc(bank, io) => format!("HDIOLC:{bank}:{io}"),
                     BondPin::Gt(bank, pad) => match pad {
                         GtPin::RxP(i) => format!("GT{bank}_RXP{i}"),
                         GtPin::RxN(i) => format!("GT{bank}_RXN{i}"),