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4 changes: 2 additions & 2 deletions _sources/xilinx/spartan3/structure.rst.txt
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.. _spartan3-geometry:

Device geomerey
################
Device geometry
###############

Spartan 3 geometry is largely the same as Virtex 2. The changes are:

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2 changes: 1 addition & 1 deletion xilinx/index.html
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Expand Up @@ -104,7 +104,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
</li>
<li class="toctree-l1"><a class="reference internal" href="spartan3/index.html">Xilinx Spartan 3 FPGAs</a><ul>
<li class="toctree-l2"><a class="reference internal" href="spartan3/intro.html">Introduction</a></li>
<li class="toctree-l2"><a class="reference internal" href="spartan3/structure.html">Device geomerey</a></li>
<li class="toctree-l2"><a class="reference internal" href="spartan3/structure.html">Device geometry</a></li>
<li class="toctree-l2"><a class="reference internal" href="spartan3/interconnect.html">General interconnect</a></li>
<li class="toctree-l2"><a class="reference internal" href="spartan3/clb.html">Configurable Logic Block β€” Spartan 3, Virtex 4</a></li>
<li class="toctree-l2"><a class="reference internal" href="spartan3/dsp.html">DSP β€” Spartan 3A DSP, Spartan 6</a></li>
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2 changes: 1 addition & 1 deletion xilinx/spartan3/clb.html
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<li class="toctree-l2"><a class="reference internal" href="../virtex2/index.html">Xilinx Virtex 2 FPGAs</a></li>
<li class="toctree-l2 current"><a class="reference internal" href="index.html">Xilinx Spartan 3 FPGAs</a><ul class="current">
<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geomerey</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
<li class="toctree-l3"><a class="reference internal" href="interconnect.html">General interconnect</a></li>
<li class="toctree-l3 current"><a class="current reference internal" href="#">Configurable Logic Block β€” Spartan 3, Virtex 4</a><ul>
<li class="toctree-l4"><a class="reference internal" href="#bitstream">Bitstream</a></li>
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2 changes: 1 addition & 1 deletion xilinx/spartan3/clock.html
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<li class="toctree-l2"><a class="reference internal" href="../virtex2/index.html">Xilinx Virtex 2 FPGAs</a></li>
<li class="toctree-l2 current"><a class="reference internal" href="index.html">Xilinx Spartan 3 FPGAs</a><ul class="current">
<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geomerey</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
<li class="toctree-l3"><a class="reference internal" href="interconnect.html">General interconnect</a></li>
<li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block β€” Spartan 3, Virtex 4</a></li>
<li class="toctree-l3"><a class="reference internal" href="dsp.html">DSP β€” Spartan 3A DSP, Spartan 6</a></li>
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2 changes: 1 addition & 1 deletion xilinx/spartan3/dsp.html
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<li class="toctree-l2"><a class="reference internal" href="../virtex2/index.html">Xilinx Virtex 2 FPGAs</a></li>
<li class="toctree-l2 current"><a class="reference internal" href="index.html">Xilinx Spartan 3 FPGAs</a><ul class="current">
<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geomerey</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
<li class="toctree-l3"><a class="reference internal" href="interconnect.html">General interconnect</a></li>
<li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block β€” Spartan 3, Virtex 4</a></li>
<li class="toctree-l3 current"><a class="current reference internal" href="#">DSP β€” Spartan 3A DSP, Spartan 6</a><ul>
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4 changes: 2 additions & 2 deletions xilinx/spartan3/index.html
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<li class="toctree-l2"><a class="reference internal" href="../virtex2/index.html">Xilinx Virtex 2 FPGAs</a></li>
<li class="toctree-l2 current"><a class="current reference internal" href="#">Xilinx Spartan 3 FPGAs</a><ul>
<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geomerey</a></li>
<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
<li class="toctree-l3"><a class="reference internal" href="interconnect.html">General interconnect</a></li>
<li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block β€” Spartan 3, Virtex 4</a></li>
<li class="toctree-l3"><a class="reference internal" href="dsp.html">DSP β€” Spartan 3A DSP, Spartan 6</a></li>
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<li class="toctree-l2"><a class="reference internal" href="intro.html#device-table">Device table</a></li>
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<li class="toctree-l2"><a class="reference internal" href="structure.html#primary-vertical-clock-spine">Primary vertical clock spine</a></li>
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6 changes: 3 additions & 3 deletions xilinx/spartan3/interconnect.html
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<li class="toctree-l2 current"><a class="reference internal" href="index.html">Xilinx Spartan 3 FPGAs</a><ul class="current">
<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
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<li class="toctree-l4"><a class="reference internal" href="#bitstream-interconnect-tiles">Bitstream β€” interconnect tiles</a></li>
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<section id="device-geomerey">
<span id="spartan3-geometry"></span><h1>Device geomerey<a class="headerlink" href="#device-geomerey" title="Link to this heading"></a></h1>
<section id="device-geometry">
<span id="spartan3-geometry"></span><h1>Device geometry<a class="headerlink" href="#device-geometry" title="Link to this heading"></a></h1>
<p>Spartan 3 geometry is largely the same as Virtex 2. The changes are:</p>
<ul class="simple">
<li><p>in addition to the primary vertical clock spine, there are now two secondary vertical clock spines that distribute clocks to <code class="docutils literal notranslate"><span class="pre">GCLKH</span></code> tiles; there is also the new horizontal clock spine that connects them together</p></li>
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