ise_hammer: 4v IO.

Cargo.toml

@@ -120,7 +120,7 @@ assert_matches = "1.5"
 serde = { version = "1.0", features = ["derive"] }
 serde_json = "1.0"
 indexmap = { version = "2", features = ["serde"] }
-ndarray = { version = "0.15", features = ["serde"] }
+ndarray = { version = "0.16", features = ["serde"] }
 enum-map = { version = "2.4", features = ["serde"] }
 bitvec = { version = "1.0", features = ["serde"] }
 itertools = "0.13"

docs/gen_xilinx.py

@@ -322,3 +322,13 @@ def emit_dev_table_string(f, name):
                                "PLL:PLL_CP_REPL",
                                "PLL:PLL_RES",
                                "PLL:PLL_LFHF")
+
+    if kind == "xc4v":
+        emit_misc_table("xilinx/gen/xc4v-iostd-misc.html", "IOSTD:OUTPUT_MISC")
+        emit_misc_table("xilinx/gen/xc4v-iostd-drive.html", "IOSTD:PDRIVE", "IOSTD:NDRIVE")
+        emit_misc_table("xilinx/gen/xc4v-iostd-slew.html", "IOSTD:PSLEW", "IOSTD:NSLEW")
+        emit_misc_table("xilinx/gen/xc4v-iostd-lvds.html", "IOSTD:LVDS_T", "IOSTD:LVDS_C")
+        emit_misc_table("xilinx/gen/xc4v-iostd-lvdsbias.html", "IOSTD:LVDSBIAS")
+        emit_misc_table("xilinx/gen/xc4v-iostd-dci-lvdiv2.html", "IOSTD:DCI:LVDIV2")
+        emit_misc_table("xilinx/gen/xc4v-iostd-dci-mask-term-vcc.html", "IOSTD:DCI:PMASK_TERM_VCC")
+        emit_misc_table("xilinx/gen/xc4v-iostd-dci-mask-term-split.html", "IOSTD:DCI:PMASK_TERM_SPLIT", "IOSTD:DCI:NMASK_TERM_SPLIT")

docs/xilinx/virtex2/index.rst

@@ -8,7 +8,7 @@ Virtex 2
    :caption: Contents:
 
    intro
-   structure
+   geometry
    interconnect
    clb
    bram

docs/xilinx/virtex4/clock.rst

@@ -157,3 +157,19 @@ IO clock nodes
 
 .. raw:: html
    :file: ../gen/tile-xc4v-HCLK_MGT.html
+
+
+I/O standard data
+=================
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-lvdsbias.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-dci-lvdiv2.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-dci-mask-term-vcc.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-dci-mask-term-split.html

docs/xilinx/virtex4/geometry.rst

@@ -0,0 +1,170 @@
+.. _virtex4-geometry:
+
+Device geometry
+###############
+
+
+General structure
+=================
+
+Virtex 4 devices are the first to use fully columnar architecture — as opposed to earlier devices that had I/O ring surrounding the device, Virtex 4 devices are made almost entirely of fully uniform columns consisting of a single kind of tiles.
+
+Virtex 4 devices are also divided in "regions". A region is always exactly 16 interconnect tiles high. The device always has a height that is a multiple of 32 interconnect tiles, or 2 regions. In addition to the 16 interconnect rows, each region has a special HCLK row running through the middle (between rows 7 and 8), which is not counted in the row numbering.
+
+The exact sequence of columns varies with the device. The main available column types are:
+
+- CLB column: contains ``CLB`` tiles, one for every interconnect tile.
+- BRAM column: contains ``BRAM`` tiles, one for every 4 interconnect tiles (ie. 4 ``BRAM`` tiles per region)
+- DSP column: contains ``DSP`` tiles, one for every 4 interconnect tiles (ie. 4 ``DSP`` tiles per region)
+- IO column: contains ``IO`` tiles, one for every interconnect tile; also contains special ``HCLK_IOIS_*`` tiles in the HCLK rows
+- the center column: there is exactly one of those per device; it contains a mixture of ``CFG``, ``IO``, ``DCM``, ``CCM``, ``SYSMON`` tiles
+- MGT column: contains ``MGT`` tiles, one for every 2 regions (ie. one for every 32 interconnect tiles)
+
+Each of the above types of columns is colocated with a single interconnect column. The interconnect column consists of:
+
+- ``INT`` tiles, one per interconnect row (16 per region)
+- ``INTF`` tiles, one for every ``INT`` tile, except for ``INT`` tiles associated with ``CLB`` tiles
+- ``HCLK`` tiles, one per region (located in the HCLK row)
+
+Additionally, there are two special kinds of columns that are not counted in the normal column numbering, and exist in between interconnect columns:
+
+- the clock column, which is always immediately to the right of the center column; it contains:
+
+  - the ``BUFGCTRL`` global clock buffers (located next to the ``CFG`` tile)
+  - ``CLK_IOB_*`` and ``CLK_DCM_*`` tiles, which multiplex and feed clock sources into the ``BUGCTRL`` primitives
+  - ``CLK_HROW`` tiles, which buffer the ``BUFGCTRL`` outputs onto HCLK rows
+
+- the vbrk columns, the significance of which is unknown; on devices with transceivers, they contain ``HCLK_MGT_REPEATER`` tiles
+
+There are always exactly two dedicated IO columns per device, and one center column which counts as the third IO column.
+
+If the MGT columns are present on the device, there are exactly two of them, and they are the leftmost and the rightmost column, with the left and right IO columns a few columns away from them.  If the MGT columns are not present, the leftmost and rightmost columns are IO columns.
+
+The other kinds of columns (CLB, BRAM, DSP) come in varying numbers, locations, and proportions, depending on device size and kind.
+
+The leftmost column of the device, whether it is MGT or IO, contains a special ``HCLK_TERM_L`` tile in every HCLK row. Likewise, the rightmost column of the device contains a special ``HCLK_TERM_R`` tile in every HCLK row.
+
+
+PowerPC holes
+-------------
+
+Some devices have hard PPC cores, which are the only exceptions to the otherwise regular structure, creating a hole in the interconnect grid.  The hole is 24 rows high and 9 columns across. The 9 columns involved are always the following, in order:
+
+- BRAM column
+- 4 CLB columns
+- BRAM column
+- 3 CLB columns
+
+The hole always starts at row 12 of a region, and ends at row 3 of another region (ie. it takes up 4 rows of one region, all 16 rows of the second region, and 4 more rows of the third region).
+
+The bottom/top rows and leftmost/rightmost columns of the hole contain interconnect tiles as usual, providing inputs/outputs to the PPC core. However, the inner area consisting of 22 rows and 7 columns has no interconnect tiles, and some interconnect lines terminate at this boundary.
+
+
+Center column
+-------------
+
+The center column consists of the following main tiles, in order:
+
+- 0 or 1 lower ``SYSMON`` tile; a ``SYSMON`` tile is 8 interconnect tiles high
+- 2 to 6 lower ``DCM`` tiles; a ``DCM`` tile is 4 interconnect tiles high
+- 0 to 2 lower ``CCM`` tiles; a ``CCM`` tile is 4 interconnect tiles high
+- 16, 32, or 48 lower ``IO`` tiles, one per interconnect tile; this block of IO tiles always starts and ends at row 8 of a region
+- the singular ``CFG`` tile, which is 16 interconnect tiles high and straddles two regions (top 8 rows of one region, then bottom 8 rows of the next region)
+- 16, 32, or 48 upper ``IO`` tiles
+- 0 to 2 upper ``CCM`` tiles
+- 2 to 6 upper ``DCM`` tiles
+- 0 or 1 upper ``SYSMON`` tile
+
+The ``CFG`` tile, or rather the midpoint of it, is considered the center point of the device. The center column is mostly symmetric around the ``CFG`` tile:
+
+- the amount of ``IO`` tiles below and above ``CFG`` is equal
+- the amount of ``CCM`` tiles below and above ``CFG`` is equal
+- the total height of ``DCM + SYSMON`` tiles below and above ``CFG`` is equal; however, there exist devices that have a ``SYSMON`` only on the bottom on the device, replacing it with two ``DCM`` tiles on the top
+
+In addition to the main tiles, the center column also has special tiles in HCLK rows:
+
+- every HCLK row completely within one of the ``SYSMON + DCM + CCM`` segments has a ``HCLK_DCM`` tile, routing clocks to the ``DCM`` and ``CCM`` tiles
+- every HCLK row completely within one of the IO segments has a ``HCLK_CENTER`` tile, responsible for IO clocking and shared IO bank functionality
+- the HCLK row on the boundary between lower ``IO`` tiles and ``CFG`` tile likewise has a ``HCLK_CENTER`` tile
+- the HCLK row on the boundary between ``CFG`` tile and upper ``IO`` tiles has a ``HCLK_CENTER_ABOVE_CFG`` tile, which is a variant of the ``HCLK_CENTER`` tile
+- the HCLK row on the boundary between lower ``DCM/CCM`` tiles and lower ``IO`` tiles has a ``HCLK_DCMIOB`` tile, combining the responsibilities of ``HCLK_CENTER`` and ``HCLK_DCM`` tiles
+- the HCLK row on the boundary between upper ``IO`` tiles and upper ``DCM/CCM`` tiles likewise has a similar ``HCLK_IOBDCM`` tile
+
+
+Spine column
+------------
+
+The spine column is responsible for global clock routing.  It has no corresponding interconnect column, borrowing interconnect from the center column where necessary.  It has the following tiles:
+
+- the ``CFG`` tile occupies both the center column and the spine column (specifically, the ``BUFGCTRL`` buffers and their multiplexers are in the spine column)
+- at the bottom: a single ``CLK_TERM_B`` tile
+- at the top: a single ``CLK_TERM_T`` tile
+- at every HCLK row: a ``CLK_HROW`` tile
+- for every pair of ``DCM`` or ``CCM`` tiles: one ``CLK_DCM_B`` or ``CLK_DCM_T`` tile (which is 8 rows high)
+- immediately above ``HCLK_DCMIOB``: one ``CLK_IOB_B`` tile (which is 16 rows high)
+- immediately below ``HCLK_IOBDCM``: one ``CLK_IOB_T`` tile (which is 16 rows high)
+
+
+Bitstream geometry
+==================
+
+The bitstream is made of frames, which come in three types:
+
+- 0: main area
+- 1: BRAM data area
+- 2: BRAM interconnect area
+
+The bitstream is now split by region — each frame covers 16 interconnect rows plus the HCLK row, and the frame size is independent of device size.
+
+Frames are identified by their type, region, major and minor numbers. The major number identifies a column (interconnect column or the clock spine), and the minor number identifies a frame within a column. The major numbers are counted separately for each type of frame.
+
+For bitstream purposes, the regions are counted using the ``CFG`` tile as the origin. Top region 0 is considered to be the region that contains the upper half of the ``CFG`` tile, top region 1 is the region above that, and so on. Bottom region 0 is considered to be the region that contains the lower half of the ``CFG`` tile, bottom region 1 is the region below that, and so on.
+
+The main area contains all columns except BRAM columns but including the clock spine, with major numbers assigned sequentially from 0 on the left, one for each column. The clock spine is included right after the center column, with a separate major number. The columns have the following widths:
+
+- CLB column: 22 frames
+- DSP column: 21 frames
+- center or IO column: 30 frames
+- MGT column: 20 frames
+- spine column: 3 frames
+
+The BRAM data area contains 64 frames for each BRAM column, in order from left. The major numbers are assigned sequentially for each BRAM column starting from 0.
+
+The BRAM interconnect area contains 20 frames for each BRAM column, in order from left. The major numbers are assigned sequentially for each BRAM column starting from 0.
+
+Each frame is exactly 1312 bits long. There are:
+
+- 80 bits per interconnect row
+- 4 bits for HCLK row
+- 12 bits for ECC
+- 16 unused bits
+
+The exact structure of the frame varies between the bottom and top halves of the device. The frames in the top half of the device have the following structure:
+
+- bits 0-639: interconnect rows 0 to 7 of the region, 80 bits per row
+- bits 640-651: ECC
+- bits 652-655: HCLK row
+- bits 656-671: unused
+- bits 672-1311: interconnect rows 8 to 15 of the region, 80 bits per row
+
+The frames in the bottom half of the device are almost but not entirely flipped — the bits corresponding to the interconnect rows are completely mirrored upside-down, but the bits corresponding to the ECC and HCLK row stay in the same place:
+
+- bits 0-639: interconnect rows 15 to 8 of the region, 80 bits per row, with all bits in reverse order
+- bits 640-651: ECC
+- bits 652-655: HCLK row
+- bits 656-671: unused
+- bits 672-1311: interconnect rows 7 to 0 of the region, 80 bits per row, with all bits in reverse order
+
+Every interconnect tile thus corresponds to a bitstream tile that is 20×80 to 30×80 bits. The actual interconnect tile is 19×80 bits, occupying the first 19 frames of the column. The remaining frames, as well as unused space in frame 19, are used for configuring the associated primitive tile.
+
+The HCLK row has smaller bitstream tiles, 20×4 to 30×4 bits in size.
+
+The spine column also has smaller bitstream tiles, 3×80 in size, as well as the extra-small 3×4 tiles on intersections with HCLK rows.
+
+The BRAM data tiles are 64×320 bits in size (covering the height of 4 interconnect rows). The area at intersection with HCLK rows is unused.
+
+
+ECC
+---
+
+.. todo:: reverse, document

docs/xilinx/virtex4/index.rst

@@ -7,6 +7,7 @@ Virtex 4
    :maxdepth: 2
    :caption: Contents:
 
+   geometry
    interconnect
    clb
    bram

docs/xilinx/virtex4/io.rst

@@ -2,8 +2,122 @@ Input/Output
 ############
 
 
+I/O banks and special functions
+===============================
+
+Virtex 4 devices have exactly three I/O columns:
+
+- the left I/O column, containing only IO tiles; if the device has no transceivers, it is the leftmost column of the device; otherwise, it is somewhat to the right of the left GT column
+- the center column, part of which contains IO tiles; the IO tiles in this column come in two segments:
+
+  - the lower segment, between lower DCMs/CCMs and the configuration center
+  - the upper segment, between the configuration center and the upper DCMs/CCMs
+
+- the right I/O column, containing only IO tiles; if the device has no transceivers, it is the rightmost column of the device; otherwise, it is somewhat to the left of the right GT column
+
+Virtex 4 has the following banks:
+
+- bank 0 is the configuration bank; it contains only dedicated configuration I/O pins, as follows:
+
+  - ``CCLK``
+  - ``CS_B``
+  - ``DONE``
+  - ``DOUT_BUSY``
+  - ``D_IN``
+  - ``HSWAP_EN``
+  - ``INIT``
+  - ``M0``
+  - ``M1``
+  - ``M2``
+  - ``PROGRAM_B``
+  - ``PWRDWN_B``
+  - ``RDWR_B``
+  - ``TCK``
+  - ``TDI``
+  - ``TDO``
+  - ``TMS``
+
+  bank 0 is not associated with any IO tiles
+
+- banks 1-4 are central column banks, with no support for true differential output; they are:
+
+  - bank 1: right above configuration center; has 8, 24, or 40 I/O tiles
+  - bank 2: right below configuration center; has 8, 24, or 40 I/O tiles
+  - bank 3: above bank 1, below top DCMs/CCMs; always has 8 I/O tiles
+  - bank 4: below bank 2, above bottom DCMs/CCMs; always has 8 I/O tiles
+
+- banks 5-16: left and right column banks; the number of present banks in these column varies between devices, but each bank has a constant size of 32 I/O tiles (ie. is two regions high); the HCLK tile in bottom region of the bank contains DCI control circuitry, while the HCLK tile in top region of the bank contains contains LVDS output circuitry
+
+  - odd-numbered banks belong to the left column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
+
+    - 4 regions: 7, 5
+    - 6 regions: 7, 9, 5
+    - 8 regions: 7, 11, 9, 5
+    - 10 regions: 7, 11, 13, 9, 5
+    - 12 regions: 7, 11, 15, 13, 9, 5
+
+  - even-numbered banks belong to the right column; the banks, in order from the bottom, will be numbered as follows depending on height of the device:
+
+    - 4 regions: 8, 6
+    - 6 regions: 8, 10, 6
+    - 8 regions: 8, 12, 10, 6
+    - 10 regions: 8, 12, 14, 10, 6
+    - 12 regions: 8, 12, 16, 14, 10, 6
+
+All IOBs in the device are grouped into differential pairs, one pair per IO tile.  ``IOB1`` is the "true" pin of the pair, while ``IOB0`` is the "complemented" pin.  Differential input is supported on all pins of the device.  True differential output is supported only in the left and right columns, in all tiles except for rows 7 and 8 of every region (ie. except the "clock-capable" pads).
+
+``IOB1`` pads next to the HCLK row (that is, in row 7 and 8 of every clock region) are considered "clock-capable". They can drive ``BUFIO`` and ``BUFR`` buffers via dedicated connections. While Xilinx documentation also considers ``IOB0`` pads clock-capable, this only means that they can be used together with ``IOB1`` as a differential pair.
+
+The 16 bottommost ``IOB1`` pads and 16 topmost ``IOB1`` pads in the central column are considered "global clock-capable". They can drive ``BUFGCTRL`` buffers and ``DCM`` primitives via dedicated connections.  Likewise, Xilinx considers ``IOB0`` pads to be clock-capable, but they can only drive clocks as part of differential pair with ``IOB1``.
+
+The ``IOB0`` in rows 4 and 12 of every region is capable of being used as a VREF pad.
+
+Each bank, with some exceptions on the smaller devices, has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on ``IOB0`` and VRN located on ``IOB1``. The relevant tile is located as follows:
+
+- bank 1, if the bank has 8 I/O tiles: DCI is not supported in this bank
+- bank 1, if the bank has 24 I/O tiles: row 14 of the bank (row 6 of the topmost region of the bank)
+- bank 1, if the bank has 40 I/O tiles: row 30 of the bank (row 6 of the topmost region of the bank)
+- bank 2, if the bank has 8 I/O tiles: DCI is not supported in this bank
+- bank 2, if the bank has 24 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
+- bank 2, if the bank has 40 I/O tiles: row 9 of the bank (row 9 of the bottom region of the bank)
+- bank 3: row 6 of the bank (row 6 of the region)
+- bank 4: row 1 of the bank (row 9 of the region)
+- banks 5-16: row 9 of the bank (row 9 of the bottom region of the bank)
+
+In parallel configuration modes, some I/O pads in banks 1 and 2 are borrowed for configuration use, as the parallel data pins:
+
+- ``D[i]``, ``i % 2 == 0``, ``0 <= i < 16``: ``IOB0`` of row ``i / 2`` of topmost region of bank 2
+- ``D[i]``, ``i % 2 == 1``, ``0 <= i < 16``: ``IOB1`` of row ``(i - 1) / 2`` of topmost region of bank 2
+- ``D[i]``, ``i % 2 == 0``, ``16 <= i < 32``: ``IOB0`` of row ``i / 2`` of bottom region of bank 1 (or, row ``(i - 16) / 2`` of the bank)
+- ``D[i]``, ``i % 2 == 1``, ``16 <= i < 32``: ``IOB1`` of row ``(i - 1) / 2`` of bottom region of bank 1 (or, row ``(i - 17) / 2`` of the bank)
+
+Every ``SYSMON`` present on the device can use up to seven IOB pairs from the left I/O column as auxiliary analog differential inputs. The ``VPx`` input corresponds to ``IOB1`` and ``VNx`` corresponds to ``IOB0`` within the same tile. The IOBs are in the following tiles, where ``r`` is the bottom row of the ``SYSMON``:
+
+- ``VP1/VN1``: left I/O column, row ``r``
+- ``VP2/VN2``: left I/O column, row ``r + 1``
+- ``VP3/VN3``: left I/O column, row ``r + 2``
+- ``VP4/VN4``: left I/O column, row ``r + 3``
+- ``VP5/VN5``: left I/O column, row ``r + 5``
+- ``VP6/VN6``: left I/O column, row ``r + 6``
+- ``VP7/VN7``: left I/O column, row ``r + 7``
+
+Row ``r + 4`` is not used as ``SYSMON`` input — the "analog function" of that pin is considered to be VREF instead (they are controlled by the same bit).
+
+
 Bitstream
 =========
 
 .. raw:: html
-   :file: ../gen/tile-xc4v-IOIS.html
+   :file: ../gen/xc4v-iostd-drive.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-slew.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-misc.html
+
+.. raw:: html
+   :file: ../gen/xc4v-iostd-lvds.html
+
+.. raw:: html
+   :file: ../gen/tile-xc4v-IO.html