Skip to content

Commit

Permalink
6s pll
Browse files Browse the repository at this point in the history
  • Loading branch information
@wanda-phi
wanda-phi committed Aug 2, 2024
1 parent 7dc1c49 commit 5f6ed28
Show file tree
Hide file tree
Showing 14 changed files with 1,160 additions and 118 deletions.
2 changes: 1 addition & 1 deletion databases/xc6s-tiledb.json
View file

Large diffs are not rendered by default.

105 changes: 63 additions & 42 deletions docs/gen_xilinx.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
with open(f"../databases/{kind}-tiledb.json") as dbf:
db = json.load(dbf)

def emit_misc_table_bitvec(fname, *prefixes):
def emit_misc_table(fname, *prefixes):
items = []
for name, data in db["misc_data"].items():
if name.startswith(prefixes[0] + ":"):
Expand All @@ -14,7 +14,10 @@ def emit_misc_table_bitvec(fname, *prefixes):
for pref in prefixes:
xname = pref + ":" + name
d = db["misc_data"][xname]
lens.append(len(d))
if isinstance(d, list):
lens.append(len(d))
else:
lens.append(-1)
data.append(d)
items.append((name, data))
if not items:
Expand All @@ -23,19 +26,26 @@ def emit_misc_table_bitvec(fname, *prefixes):
f.write("<table class=\"docutils align-default\">\n")
f.write(f"<tr><th rowspan=\"2\">Name</th>")
for (pref, l) in zip(prefixes, lens):
f.write(f"<th colspan=\"{l}\">{pref}</th>")
if l == -1:
f.write(f"<th colspan=\"{l}\">{pref}</th>")
else:
f.write(f"<th rowspan=\"2\">{pref}</th>")
f.write(f"</tr>\n")
f.write(f"<tr>")
for l in lens:
for i in reversed(range(l)):
f.write(f"<th>[{i}]</th>")
if l != -1:
for i in reversed(range(l)):
f.write(f"<th>[{i}]</th>")
f.write(f"</tr>\n")
for name, data in items:
f.write(f"<tr><td>{name}</td>")
for (d, l) in zip(data, lens):
assert len(d) == l
for i in reversed(range(l)):
f.write(f"<td>{int(d[i])}</td>")
if l == -1:
f.write(f"<td>{d}</td>")
else:
assert len(d) == l
for i in reversed(range(l)):
f.write(f"<td>{int(d[i])}</td>")
f.write(f"</tr>\n")
f.write(f"</table>\n")

Expand Down Expand Up @@ -224,45 +234,45 @@ def emit_dev_table_string(f, name):
f.write("</table>\n")

if kind == "xc2v":
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-drive.html", "IOSTD:V2:PDRIVE", "IOSTD:V2:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-slew.html", "IOSTD:V2:SLEW")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-output-misc.html", "IOSTD:V2:OUTPUT_MISC")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-output-diff.html", "IOSTD:V2:OUTPUT_DIFF")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-lvdsbias.html", "IOSTD:V2:LVDSBIAS")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-dci-term-split.html", "IOSTD:V2:TERM_SPLIT")
emit_misc_table_bitvec("xilinx/gen/xc2v-iostd-dci-term-vcc.html", "IOSTD:V2:TERM_VCC")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-drive.html", "IOSTD:V2P:PDRIVE", "IOSTD:V2P:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-slew.html", "IOSTD:V2P:SLEW")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-output-misc.html", "IOSTD:V2P:OUTPUT_MISC")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-output-diff.html", "IOSTD:V2P:OUTPUT_DIFF")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-lvdsbias.html", "IOSTD:V2P:LVDSBIAS")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-dci-term-split.html", "IOSTD:V2P:TERM_SPLIT")
emit_misc_table_bitvec("xilinx/gen/xc2vp-iostd-dci-term-vcc.html", "IOSTD:V2P:TERM_VCC")
emit_misc_table_bitvec("xilinx/gen/xc2v-gt10-PMA_SPEED.html", "GT10:PMA_SPEED")
emit_misc_table("xilinx/gen/xc2v-iostd-drive.html", "IOSTD:V2:PDRIVE", "IOSTD:V2:NDRIVE")
emit_misc_table("xilinx/gen/xc2v-iostd-slew.html", "IOSTD:V2:SLEW")
emit_misc_table("xilinx/gen/xc2v-iostd-output-misc.html", "IOSTD:V2:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc2v-iostd-output-diff.html", "IOSTD:V2:OUTPUT_DIFF")
emit_misc_table("xilinx/gen/xc2v-iostd-lvdsbias.html", "IOSTD:V2:LVDSBIAS")
emit_misc_table("xilinx/gen/xc2v-iostd-dci-term-split.html", "IOSTD:V2:TERM_SPLIT")
emit_misc_table("xilinx/gen/xc2v-iostd-dci-term-vcc.html", "IOSTD:V2:TERM_VCC")
emit_misc_table("xilinx/gen/xc2vp-iostd-drive.html", "IOSTD:V2P:PDRIVE", "IOSTD:V2P:NDRIVE")
emit_misc_table("xilinx/gen/xc2vp-iostd-slew.html", "IOSTD:V2P:SLEW")
emit_misc_table("xilinx/gen/xc2vp-iostd-output-misc.html", "IOSTD:V2P:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc2vp-iostd-output-diff.html", "IOSTD:V2P:OUTPUT_DIFF")
emit_misc_table("xilinx/gen/xc2vp-iostd-lvdsbias.html", "IOSTD:V2P:LVDSBIAS")
emit_misc_table("xilinx/gen/xc2vp-iostd-dci-term-split.html", "IOSTD:V2P:TERM_SPLIT")
emit_misc_table("xilinx/gen/xc2vp-iostd-dci-term-vcc.html", "IOSTD:V2P:TERM_VCC")
emit_misc_table("xilinx/gen/xc2v-gt10-PMA_SPEED.html", "GT10:PMA_SPEED")

with open("xilinx/gen/xc2v-dcm-deskew-adjust.html", "w") as f:
emit_dev_table_bitvec(f, "DCM:DESKEW_ADJUST")

if kind == "xc3s":
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-drive.html", "IOSTD:S3:PDRIVE", "IOSTD:S3:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-slew.html", "IOSTD:S3:SLEW")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-output-misc.html", "IOSTD:S3:OUTPUT_MISC")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-output-diff.html", "IOSTD:S3:OUTPUT_DIFF")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-lvdsbias.html", "IOSTD:S3:LVDSBIAS")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-dci-term-split.html", "IOSTD:S3:TERM_SPLIT")
emit_misc_table_bitvec("xilinx/gen/xc3s-iostd-dci-term-vcc.html", "IOSTD:S3:TERM_VCC")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-drive.html", "IOSTD:S3E:PDRIVE", "IOSTD:S3E:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-slew.html", "IOSTD:S3E:SLEW")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-output-misc.html", "IOSTD:S3E:OUTPUT_MISC")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-output-diff.html", "IOSTD:S3E:OUTPUT_DIFF")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-lvdsbias-0.html", "IOSTD:S3E:LVDSBIAS_0")
emit_misc_table_bitvec("xilinx/gen/xc3se-iostd-lvdsbias-1.html", "IOSTD:S3E:LVDSBIAS_1")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-tb-drive.html", "IOSTD:S3A.TB:PDRIVE", "IOSTD:S3A.TB:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-tb-slew.html", "IOSTD:S3A.TB:PSLEW", "IOSTD:S3A.TB:NSLEW")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-tb-output-diff.html", "IOSTD:S3A.TB:OUTPUT_DIFF")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-lr-drive.html", "IOSTD:S3A.LR:PDRIVE", "IOSTD:S3A.LR:NDRIVE")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-lr-slew.html", "IOSTD:S3A.LR:PSLEW", "IOSTD:S3A.LR:NSLEW")
emit_misc_table_bitvec("xilinx/gen/xc3sa-iostd-tb-lvdsbias.html", "IOSTD:S3A.TB:LVDSBIAS")
emit_misc_table("xilinx/gen/xc3s-iostd-drive.html", "IOSTD:S3:PDRIVE", "IOSTD:S3:NDRIVE")
emit_misc_table("xilinx/gen/xc3s-iostd-slew.html", "IOSTD:S3:SLEW")
emit_misc_table("xilinx/gen/xc3s-iostd-output-misc.html", "IOSTD:S3:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc3s-iostd-output-diff.html", "IOSTD:S3:OUTPUT_DIFF")
emit_misc_table("xilinx/gen/xc3s-iostd-lvdsbias.html", "IOSTD:S3:LVDSBIAS")
emit_misc_table("xilinx/gen/xc3s-iostd-dci-term-split.html", "IOSTD:S3:TERM_SPLIT")
emit_misc_table("xilinx/gen/xc3s-iostd-dci-term-vcc.html", "IOSTD:S3:TERM_VCC")
emit_misc_table("xilinx/gen/xc3se-iostd-drive.html", "IOSTD:S3E:PDRIVE", "IOSTD:S3E:NDRIVE")
emit_misc_table("xilinx/gen/xc3se-iostd-slew.html", "IOSTD:S3E:SLEW")
emit_misc_table("xilinx/gen/xc3se-iostd-output-misc.html", "IOSTD:S3E:OUTPUT_MISC")
emit_misc_table("xilinx/gen/xc3se-iostd-output-diff.html", "IOSTD:S3E:OUTPUT_DIFF")
emit_misc_table("xilinx/gen/xc3se-iostd-lvdsbias-0.html", "IOSTD:S3E:LVDSBIAS_0")
emit_misc_table("xilinx/gen/xc3se-iostd-lvdsbias-1.html", "IOSTD:S3E:LVDSBIAS_1")
emit_misc_table("xilinx/gen/xc3sa-iostd-tb-drive.html", "IOSTD:S3A.TB:PDRIVE", "IOSTD:S3A.TB:NDRIVE")
emit_misc_table("xilinx/gen/xc3sa-iostd-tb-slew.html", "IOSTD:S3A.TB:PSLEW", "IOSTD:S3A.TB:NSLEW")
emit_misc_table("xilinx/gen/xc3sa-iostd-tb-output-diff.html", "IOSTD:S3A.TB:OUTPUT_DIFF")
emit_misc_table("xilinx/gen/xc3sa-iostd-lr-drive.html", "IOSTD:S3A.LR:PDRIVE", "IOSTD:S3A.LR:NDRIVE")
emit_misc_table("xilinx/gen/xc3sa-iostd-lr-slew.html", "IOSTD:S3A.LR:PSLEW", "IOSTD:S3A.LR:NSLEW")
emit_misc_table("xilinx/gen/xc3sa-iostd-tb-lvdsbias.html", "IOSTD:S3A.TB:LVDSBIAS")

with open("xilinx/gen/xc3s-bram-opts.html", "w") as f:
emit_dev_table_bitvec(f, "BRAM:DDEL_A_DEFAULT")
Expand Down Expand Up @@ -293,3 +303,14 @@ def emit_dev_table_string(f, name):
if kind == "xc6s":
with open("xilinx/gen/xc6s-pci-ce-delay.html", "w") as f:
emit_dev_table_string(f, "PCI_CE_DELAY")
emit_misc_table("xilinx/gen/xc6s-pll-lock.html",
"PLL:PLL_LOCK_REF_DLY",
"PLL:PLL_LOCK_FB_DLY",
"PLL:PLL_LOCK_CNT",
"PLL:PLL_LOCK_SAT_HIGH",
"PLL:PLL_UNLOCK_CNT")
emit_misc_table("xilinx/gen/xc6s-pll-filter.html",
"PLL:PLL_CP",
"PLL:PLL_CP_REPL",
"PLL:PLL_RES",
"PLL:PLL_LFHF")
1 change: 1 addition & 0 deletions docs/xilinx/spartan6/index.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,5 +16,6 @@ Spartan 6
pcie
gtp
dcm
pll
corner
config
22 changes: 22 additions & 0 deletions docs/xilinx/spartan6/pll.rst
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
.. _spartan6-pll:

Phase-locked loop
#################

.. todo:: document


Bitstream
=========

.. raw:: html
:file: ../gen/tile-xc6s-CMT_PLL.html

Tables
======

.. raw:: html
:file: ../gen/xc6s-pll-lock.html

.. raw:: html
:file: ../gen/xc6s-pll-filter.html
7 changes: 4 additions & 3 deletions prjcombine_ise_hammer/src/clk/spartan6.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1096,16 +1096,17 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
"REG_T" => edev.grid.gts != Gts::None,
_ => unreachable!(),
};
if has_gt {
if has_gt && !ctx.device.name.starts_with("xa") {
ctx.collect_bit(tile, bel, "MISR_ENABLE", "1");
let mut diff = ctx.state.get_diff(tile, bel, "MISR_ENABLE_RESET", "1");
diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "MISR_ENABLE"), true, false);
ctx.tiledb
.insert(tile, bel, "MISR_RESET", xlat_bitvec(vec![diff]));

} else {
ctx.state.get_diff(tile, bel, "MISR_ENABLE", "1").assert_empty();
ctx.state.get_diff(tile, bel, "MISR_ENABLE_RESET", "1").assert_empty();
// they're sometimes working, sometimes not, in nonsensical ways; just kill them
ctx.state.get_diff(tile, bel, "MISR_ENABLE", "1");
ctx.state.get_diff(tile, bel, "MISR_ENABLE_RESET", "1");
}
}
}
Expand Down
12 changes: 6 additions & 6 deletions prjcombine_ise_hammer/src/dcm/spartan3e.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -75,28 +75,28 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
fuzz_multi!(ctx, "DLL_C", "", 32, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DLL_C_"));
], (global_xy_bin "CFG_DLL_C_*"));
fuzz_multi!(ctx, "DLL_S", "", 32, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DLL_S_"));
], (global_xy_bin "CFG_DLL_S_*"));
fuzz_multi!(ctx, "DFS_C", "", 12, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DFS_C_"));
], (global_xy_bin "CFG_DFS_C_*"));
fuzz_multi!(ctx, "DFS_S", "", 76, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DFS_S_"));
], (global_xy_bin "CFG_DFS_S_*"));
fuzz_multi!(ctx, "INTERFACE", "", 16, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_INTERFACE_"));
], (global_xy_bin "CFG_INTERFACE_*"));
if vreg.is_none() {
fuzz_multi!(ctx, "VREG", "", 36, [
(global_mutex "DCM", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_REG_"));
], (global_xy_bin "CFG_REG_*"));
}
for pin in [
"RST",
Expand Down
28 changes: 18 additions & 10 deletions prjcombine_ise_hammer/src/dcm/spartan6.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ use unnamed_entity::EntityId;
use crate::{
backend::{IseBackend, PinFromKind},
diff::{xlat_bitvec, xlat_enum_default, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
fuzz::FuzzCtx,
fuzz_enum, fuzz_enum_suffix, fuzz_inv, fuzz_multi, fuzz_one, fuzz_one_extras,
};
Expand Down Expand Up @@ -43,35 +43,35 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
fuzz_multi!(ctx, "DLL_C", "", 32, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DLL_C_"));
], (global_xy_bin "CFG_DLL_C_*"));
fuzz_multi!(ctx, "DLL_S", "", 32, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DLL_S_"));
], (global_xy_bin "CFG_DLL_S_*"));
fuzz_multi!(ctx, "DFS_C", "", 3, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DFS_C_"));
], (global_xy_bin "CFG_DFS_C_*"));
fuzz_multi!(ctx, "DFS_S", "", 87, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_DFS_S_"));
], (global_xy_bin "CFG_DFS_S_*"));
fuzz_multi!(ctx, "INTERFACE", "", 40, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_INTERFACE_"));
], (global_xy_bin "CFG_INTERFACE_*"));
fuzz_multi!(ctx, "OPT_INV", "", 20, [
(global_mutex "CMT", "CFG"),
(mode "DCM")
], (global_xy_bin "CFG_OPT_INV_"));
], (global_xy_bin "CFG_OPT_INV_*"));
fuzz_multi!(ctx, "REG", "", 9, [
(global_mutex "CMT", format!("CFG_DCM{i}")),
(mode "DCM")
], (global_xy_bin "CFG_REG_"));
], (global_xy_bin "CFG_REG_*"));
fuzz_multi!(ctx, "BG", "", 11, [
(global_mutex "CMT", format!("CFG_DCM{i}")),
(mode "DCM")
], (global_xy_bin "CFG_BG_"));
], (global_xy_bin "CFG_BG_*"));

let obel_dcm = BelId::from_idx(i ^ 1);
for opin in ["CLKIN", "CLKIN_TEST"] {
Expand All @@ -80,12 +80,20 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
("CKINT1", "CLKIN_CKINT1"),
("CLK_FROM_PLL", "CLK_FROM_PLL"),
] {
let related_pll = TileRelation::Delta(0, 16, backend.egrid.db.get_node("CMT_PLL"));
let bel_pll = BelId::from_idx(0);
fuzz_one!(ctx, format!("MUX.{opin}"), val, [
(mode "DCM"),
(global_mutex "CMT", "TEST"),
(mutex "CLKIN_OUT", opin),
(mutex "CLKIN_IN", pin),
(tile_mutex "CLKIN_BEL", format!("DCM{i}"))
(tile_mutex "CLKIN_BEL", format!("DCM{i}")),
(related related_pll,
(pip (bel_pin bel_pll, "CLKOUTDCM0"), (bel_pin bel_pll, format!("CLK_TO_DCM{i}")))
),
(related related_pll,
(mutex "CLK_TO_DCM", "USE")
)
], [
(pip (pin pin), (pin opin))
]);
Expand Down
Loading

0 comments on commit 5f6ed28

Please sign in to comment.