ise_hammer: fpgacore.

docs/gen_xilinx.py

@@ -1,6 +1,6 @@
 import json
 
-for kind in ["xc5k", "xcv", "xc2v", "xc3s", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"]:
+for kind in ["xc5k", "xcv", "xc2v", "xc3s", "xcexf", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"]:
     with open(f"../databases/{kind}-tiledb.json") as dbf:
         db = json.load(dbf)
 

docs/xilinx/fpgacore/clb.rst

@@ -0,0 +1,39 @@
+.. _fpgacore-clb:
+
+Configurable Logic Block
+########################
+
+The CLB is identical to Spartan 3.
+
+
+Bitstream
+=========
+
+The data for a CLB is located in the same bitstream tile as the associated ``INT.CLB`` tile.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLB.html
+
+
+``RESERVED_ANDOR``
+==================
+
+TODO: wtf is this even
+
+
+``RANDOR``
+----------
+
+This tile overlaps ``IOI.*``.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-RANDOR.html
+
+
+``RANDOR_INIT``
+---------------
+
+This tile overlaps top-left interconnect tile.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-RANDOR_INIT.html

docs/xilinx/fpgacore/clock.rst

@@ -0,0 +1,78 @@
+.. _fpgacore-clock:
+
+Clock interconnect
+##################
+
+.. todo:: document
+
+
+Clock source — spine bottom and top
+===================================
+
+.. todo:: document
+
+
+Bitstream — bottom tiles
+------------------------
+
+.. todo:: document
+
+
+``CLKB.FC``
++++++++++++
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLKB.FC.html
+
+
+Bitstream — top tiles
+---------------------
+
+.. todo:: document
+
+
+``CLKT.FC``
++++++++++++
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLKT.FC.html
+
+
+The ``CLKC`` clock center tile
+==============================
+
+.. todo:: document
+
+
+The ``GCLKVM`` secondary clock center tiles
+===========================================
+
+The ``GCLKVM`` tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.
+
+.. todo:: document
+
+
+``GCLKVM.S3``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-GCLKVM.S3.html
+
+
+The ``GCLKVC`` clock spine distribution tiles
+=============================================
+
+.. todo:: document
+
+
+The ``GCLKH`` clock row distribution tiles
+==========================================
+
+.. todo:: document
+
+
+``GCLKH``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-GCLKH.html

docs/xilinx/fpgacore/config.rst

@@ -0,0 +1,20 @@
+.. _fpgacore-config:
+
+Configuration registers
+#######################
+
+.. todo:: document
+
+
+``COR.FC``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-REG.COR.FC.html
+
+
+``CTL.S3``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-REG.CTL.S3.html

docs/xilinx/fpgacore/corner.rst

@@ -0,0 +1,58 @@
+.. _fpgacore-corner:
+
+Corners
+#######
+
+.. todo:: document
+
+
+Lower left
+==========
+
+.. todo:: document
+
+
+``LL.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-LL.FC.html
+
+
+Upper left
+==========
+
+.. todo:: document
+
+
+``UL.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-UL.FC.html
+
+
+Lower right
+===========
+
+.. todo:: document
+
+
+``LR.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-LR.FC.html
+
+
+Upper right
+===========
+
+.. todo:: document
+
+
+``UR.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-UR.FC.html

docs/xilinx/fpgacore/index.rst

@@ -0,0 +1,15 @@
+FPGAcore
+########
+
+.. todo:: intro document, bitstream format, other tiles, jtag, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   interconnect
+   clb
+   clock
+   io
+   corner
+   config

docs/xilinx/fpgacore/interconnect.rst

@@ -0,0 +1,29 @@
+.. _fpgacore-interconnect:
+
+General interconnect
+####################
+
+FPGAcore interconnect is identical to Spartan 3 with one exception: there are 12 long lines for each orientation instead of 24.
+
+
+Bitstream — interconnect tiles
+==============================
+
+The interconnect tiles are 19×64 bits. The space on the left is unused by the interconnect tile, and contains data for whatever primitive is associated with the interconnect tile.
+
+``INT.CLB``
+-----------
+
+Used with ``CLB`` tiles.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-INT.CLB.html
+
+
+``INT.IOI.FC``
+--------------
+
+Used with ``IOI`` tiles.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-INT.IOI.FC.html

docs/xilinx/fpgacore/io.rst

@@ -0,0 +1,53 @@
+.. _fpgacore-io:
+
+Input / Output
+##############
+
+.. todo:: document
+
+
+I/O interface
+=============
+
+.. todo:: document
+
+
+``IOI.FC``
+----------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOI.FC.html
+
+
+I/O buffers — Spartan 3
+=======================
+
+.. todo:: document
+
+
+``IOBS.FC.T``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.T.html
+
+
+``IOBS.FC.R``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.R.html
+
+
+``IOBS.FC.B``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.B.html
+
+
+``IOBS.FC.L``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.L.html

docs/xilinx/index.rst

@@ -9,6 +9,7 @@ Xilinx FPGAs
    virtex/index
    virtex2/index
    spartan3/index
+   fpgacore/index
    spartan6/index
    virtex4/index
    virtex5/index

docs/xilinx/virtex/dll.rst

@@ -1,3 +1,5 @@
+.. _virtex-dll:
+
 Delay Locked Loop
 #################
 

prjcombine_ise_dump/src/bin/dump_ise_parts.rs

@@ -65,6 +65,7 @@ fn main() -> Result<(), Box<dyn Error>> {
             "virtex2" => vec!["virtex2", "qvirtex2", "qrvirtex2"],
             "virtex2p" => vec!["virtex2p", "qvirtex2p"],
             "spartan3" => vec!["spartan3", "aspartan3"],
+            "fpgacore" => vec!["fpgacore"],
             "spartan3e" => vec!["spartan3e", "aspartan3e"],
             "spartan3a" => vec!["spartan3a", "aspartan3a"],
             "spartan3adsp" => vec!["spartan3adsp", "aspartan3adsp"],

prjcombine_ise_dump/src/partgen.rs

@@ -151,6 +151,7 @@ const PATTERNS: &[(&str, &str, &str)] = &[
     ("x[cq]2vpx?[0-9]+", "[a-z]{2}[0-9]+", "virtex2p"),
     ("xc3s[0-9]+l?", "[a-z]{2}[0-9]+", "spartan3"),
     ("xa3s[0-9]+l?", "[a-z]{2}g[0-9]+", "spartan3"),
+    ("xcexf[0-9]+", "die", "fpgacore"),
     ("xc3s[0-9]+e", "[a-z]{2}[0-9]+", "spartan3e"),
     ("xa3s[0-9]+e", "[a-z]{2}g[0-9]+", "spartan3e"),
     ("xc3s[0-9]+a", "[a-z]{2}[0-9]+", "spartan3a"),

prjcombine_ise_hammer/src/bram/spartan6.rs

@@ -6,7 +6,7 @@ use prjcombine_types::TileItem;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
+    diff::{xlat_bit, xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_multi_attr_hex, fuzz_one, fuzz_one_extras,
@@ -421,10 +421,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let diff1_h0 = ctx.state.get_diff(tile, "BRAM_H0", attr, val1);
         let diff1_h1 = ctx.state.get_diff(tile, "BRAM_H1", attr, val1);
         assert_eq!(diff1_f, diff1_h0.combine(&diff1_h1));
-        ctx.tiledb
-            .insert(tile, "BRAM_H0", attr, xlat_bitvec(vec![diff1_h0]));
-        ctx.tiledb
-            .insert(tile, "BRAM_H1", attr, xlat_bitvec(vec![diff1_h1]));
+        ctx.tiledb.insert(tile, "BRAM_H0", attr, xlat_bit(diff1_h0));
+        ctx.tiledb.insert(tile, "BRAM_H1", attr, xlat_bit(diff1_h1));
     }
     for (attr, bel, sattr) in [
         ("BW_EN_A", "BRAM_H0", "BW_EN_A_D"),
@@ -433,7 +431,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ("BW_EN_B", "BRAM_H1", "BW_EN_B_U"),
     ] {
         let diff = ctx.state.get_diff(tile, "BRAM_F", sattr, "1");
-        ctx.tiledb.insert(tile, bel, attr, xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, attr, xlat_bit(diff));
     }
 
     for (attr, bel, sattr) in [