ise_hammer: 5v misc, clk

docs/gen_xilinx.py

@@ -101,6 +101,7 @@ def emit_dev_table_string(f, name):
                     rev[key].append((name, item, None if len(item["bits"]) == 1 else j))
             for bt, (columns, rows) in enumerate(bt_dims):
                 f.write("<table class=\"docutils align-default prjcombine-tile\">\n")
+                f.write(f"<tr><th colspan=\"{columns + 1}\">{tile_name} bittile {bt}</th></tr>")
                 f.write(f"<tr><th rowspan=\"2\">Row</th><th colspan=\"{columns}\">Column</th></tr>")
                 f.write("<tr>")
                 for col in range(columns):

docs/xilinx/virtex5/center.rst

@@ -0,0 +1,12 @@
+.. _virtex5-center:
+
+Configuration Center
+####################
+
+.. todo:: document
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CFG.html

docs/xilinx/virtex5/clock.rst

@@ -0,0 +1,134 @@
+.. _virtex5-clock:
+
+Clock interconnect
+##################
+
+.. todo:: describe this madness
+
+
+``CLK_HROW``
+============
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_HROW.html
+
+
+``HCLK``
+========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK.html
+
+
+Spine muxes — IOB
+=================
+
+
+``CLK_IOB_B``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_IOB_B.html
+
+
+``CLK_IOB_T``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_IOB_T.html
+
+
+Spine muxes — CMT
+=================
+
+
+``CLK_CMT_B``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_CMT_B.html
+
+
+``CLK_CMT_T``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_CMT_T.html
+
+
+Spine muxes — MGT
+=================
+
+
+``CLK_MGT_B``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_MGT_B.html
+
+
+``CLK_MGT_T``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-CLK_MGT_T.html
+
+
+MGT clock repeater
+==================
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_BRAM_MGT.html
+
+
+IO clock nodes
+==============
+
+
+``HCLK_IOI``
+------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_IOI.html
+
+
+``HCLK_IOI_CENTER``
+-------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_IOI_CENTER.html
+
+
+``HCLK_IOI_BOTCEN``
+-------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_IOI_BOTCEN.html
+
+
+``HCLK_IOI_TOPCEN``
+-------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_IOI_TOPCEN.html
+
+
+``HCLK_IOI_CMT``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_IOI_CMT.html
+
+
+``HCLK_CMT_IOI``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_CMT_IOI.html
+
+
+``HCLK_CMT``
+------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-HCLK_CMT.html

docs/xilinx/virtex5/config.rst

@@ -0,0 +1,33 @@
+.. _virtex5-config:
+
+Configuration registers
+#######################
+
+.. todo:: document
+
+``COR``
+=======
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-REG.COR.html
+
+
+``COR1``
+========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-REG.COR1.html
+
+
+``CTL``
+=======
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-REG.CTL.html
+
+
+``TIMER``
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-REG.TIMER.html

docs/xilinx/virtex5/index.rst

@@ -7,10 +7,13 @@ Xilinx Virtex 5 FPGAs
    :maxdepth: 2
    :caption: Contents:
 
-   int
+   interconnect
    clb
    bram
    dsp
+   center
+   clock
    ppc
    emac
    pcie
+   config

prjcombine_ise_hammer/src/backend.rs

@@ -370,7 +370,7 @@ impl<'a> Backend for IseBackend<'a> {
                     _ => unreachable!(),
                 },
                 Key::Pip(tile, wa, wb) => match v {
-                    Value::None => (),
+                    Value::None | Value::Bool(false) => (),
                     Value::Bool(true) => single_pips.push(NetPip {
                         tile: tile.to_string(),
                         wire_from: wa.to_string(),

prjcombine_ise_hammer/src/bram.rs

@@ -1,5 +1,5 @@
+pub mod spartan6;
 pub mod virtex;
 pub mod virtex2;
-pub mod spartan6;
 pub mod virtex4;
 pub mod virtex5;

prjcombine_ise_hammer/src/bram/virtex5.rs

@@ -193,7 +193,8 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         ]);
         if mode != "FIFO36_72_EXP" {
             fuzz_enum_suffix!(ctx, "EN_ECC_SCRUB", mode, ["FALSE", "TRUE"], [
-                (mode mode)
+                (mode mode),
+                (global_mutex "BRAM_OPT", "NONE")
             ]);
         }
     }
@@ -306,6 +307,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         ]);
         fuzz_enum_suffix!(ctx, format!("WRITE_WIDTH_{ab}"), "RAMBFIFO18", ["0", "1", "2", "4", "9", "18"], [
             (mode "RAMBFIFO18"),
+            (attr format!("DO{ab}_REG"), "0"),
             (pin format!("WE{ab}0")),
             (pin format!("WE{ab}1")),
             (pin format!("WE{ab}2")),
@@ -827,20 +829,14 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         present_ramb18x2sdp.apply_enum_diff(item, "READ_FIRST", "WRITE_FIRST");
         present_ramb36sdp.apply_enum_diff(item, "READ_FIRST", "WRITE_FIRST");
     }
-    for attr in [
-        "WRITE_MODE_A_L",
-        "WRITE_MODE_B_L",
-    ] {
+    for attr in ["WRITE_MODE_A_L", "WRITE_MODE_B_L"] {
         let item = ctx.tiledb.item(tile, bel, attr);
         present_rambfifo18.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
         present_rambfifo18_36.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
         present_fifo36.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
         present_fifo36_72.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
     }
-    for attr in [
-        "WRITE_MODE_A_U",
-        "WRITE_MODE_B_U",
-    ] {
+    for attr in ["WRITE_MODE_A_U", "WRITE_MODE_B_U"] {
         let item = ctx.tiledb.item(tile, bel, attr);
         present_rambfifo18_36.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
         present_fifo36.apply_enum_diff(item, "NO_CHANGE", "WRITE_FIRST");
@@ -1032,20 +1028,14 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let item = ctx.extract_enum(tile, bel, &format!("{attr}.{mode}"), &["0", "1"]);
         ctx.tiledb.insert(tile, bel, hwattr, item);
     }
-    for attr in [
-        "DOA_REG_L",
-        "DOB_REG_L",
-    ] {
+    for attr in ["DOA_REG_L", "DOB_REG_L"] {
         let item = ctx.tiledb.item(tile, bel, attr);
         present_rambfifo18.apply_enum_diff(item, "1", "0");
         present_rambfifo18_36.apply_enum_diff(item, "1", "0");
         present_fifo36.apply_enum_diff(item, "1", "0");
         present_fifo36_72.apply_enum_diff(item, "1", "0");
     }
-    for attr in [
-        "DOA_REG_U",
-        "DOB_REG_U",
-    ] {
+    for attr in ["DOA_REG_U", "DOB_REG_U"] {
         let item = ctx.tiledb.item(tile, bel, attr);
         present_fifo36.apply_enum_diff(item, "1", "0");
         present_fifo36_72.apply_enum_diff(item, "1", "0");
@@ -1375,5 +1365,6 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     present_ramb36sdp.assert_empty();
 
     assert_eq!(present_fifo36, present_fifo36_72);
-    ctx.tiledb.insert(tile, bel, "IS_FIFO_U", xlat_bitvec(vec![present_fifo36]));
+    ctx.tiledb
+        .insert(tile, bel, "IS_FIFO_U", xlat_bitvec(vec![present_fifo36]));
 }

prjcombine_ise_hammer/src/ccm.rs

@@ -1 +1 @@
-pub mod virtex4;
+pub mod virtex4;

prjcombine_ise_hammer/src/ccm/virtex4.rs

@@ -482,7 +482,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     "DPM_OSCOUT2",
                     "CKINT",
                 ],
-                OcdMode::Mux
+                OcdMode::Mux,
             );
         }
     }

prjcombine_ise_hammer/src/clk.rs

@@ -1,3 +1,4 @@
-pub mod virtex2;
 pub mod spartan6;
+pub mod virtex2;
 pub mod virtex4;
+pub mod virtex5;

prjcombine_ise_hammer/src/clk/spartan6.rs

@@ -694,7 +694,12 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
             ]);
         }
     }
-    for tile in ["PCI_CE_TRUNK_BUF", "PCI_CE_V_BUF", "PCI_CE_SPLIT", "PCI_CE_H_BUF"] {
+    for tile in [
+        "PCI_CE_TRUNK_BUF",
+        "PCI_CE_V_BUF",
+        "PCI_CE_SPLIT",
+        "PCI_CE_H_BUF",
+    ] {
         if let Some(ctx) = FuzzCtx::try_new(session, backend, tile, tile, TileBits::Null) {
             fuzz_one!(ctx, "BUF", "1", [], [
                 (pip (pin "PCI_CE_I"), (pin "PCI_CE_O"))
@@ -1020,10 +1025,12 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let enable = ctx.extract_bit(tile, bel, "ENABLE", "1");
             let mut diff = ctx.state.get_diff(tile, bel, "ENABLE_NONE_SYNC", "1");
             diff.apply_bit_diff(&enable, true, false);
-            ctx.tiledb.insert(tile, bel, "ENABLE_NONE_SYNC", xlat_bit_wide(diff));
+            ctx.tiledb
+                .insert(tile, bel, "ENABLE_NONE_SYNC", xlat_bit_wide(diff));
             let mut diff = ctx.state.get_diff(tile, bel, "ENABLE_BOTH_SYNC", "1");
             diff.apply_bit_diff(&enable, true, false);
-            ctx.tiledb.insert(tile, bel, "ENABLE_BOTH_SYNC", xlat_bit_wide(diff));
+            ctx.tiledb
+                .insert(tile, bel, "ENABLE_BOTH_SYNC", xlat_bit_wide(diff));
             ctx.tiledb.insert(tile, "BUFPLL_COMMON", "ENABLE", enable);
             ctx.collect_enum_bool(tile, bel, "ENABLE_SYNC", "FALSE", "TRUE");