done with base bus

NES.qsf

@@ -50,4 +50,5 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
-set_global_assignment -name QIP_FILE system_ram.qip
+set_global_assignment -name QIP_FILE system_ram.qip
+set_global_assignment -name QIP_FILE main_pll.qip

databus.sv

@@ -0,0 +1,37 @@
+module databus (input [23:0] ADDR,
+                input        CPU_WR,
+
+                input [7:0]  CPU_DO,
+                input [7:0] SYSRAM_Q,
+                input [7:0] PRGROM_Q,
+                input [7:0] CONTROL1,
+                input [7:0] CONTROL2,
+
+                output [7:0] BUS_OUT,
+
+                output CONTROL1_EN,
+                output CONTROL2_EN,
+                output SYSRAM_EN);
+  always_comb begin
+    CONTROL1_EN = 0;
+    CONTROL2_EN = 0;
+    SYSRAM_EN = 0;
+    if (ADDR<=24'h07FF) begin
+      SYSRAM_EN = CPU_WR;
+      BUS_OUT = (CPU_WR) ? SYSRAM_Q : CPU_DO;
+    end
+
+    else if (ADDR>=24'h8000 && ADDR<=24'hFFFF)
+      BUS_OUT = PRGROM_Q;
+
+    else if (ADDR==24'h4016) begin
+      CONTROL1_EN = CPU_WR;
+      BUS_OUT = (CPU_WR) ? CONTROL1 : CPU_DO;
+    end
+
+    else if (ADDR=24'h4017) begin
+      CONTROL2_EN = CPU_WR;
+      BUS_OUT = (CPU_WR) ? CONTROL2 : CPU_DO;
+    end
+  end
+endmodule // databus

main_pll.ppf

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="MAX 10" variation_name="main_pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>

main_pll.qip

@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "main_pll.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "main_pll_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "main_pll.ppf"]